Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods

Patent metadata

Field	Value
Publication number	US-9331671-B2
Application number	US-201414283043-A
Country	US
Kind code	B2
Filing date	May 20, 2014
Priority date	May 20, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.

First claim

What is claimed is:

1. An open drain transmitter, comprising:
at least one data channel, each data channel operable to communicate data and to provide a drive current that is received over the data channel and is used in generating a harvested voltage on a harvested node, and the value of the drive current being a function of a cascode drive voltage;
a clock channel operable to communicate a clock signal and including:
a communications and power harvesting circuit operable to communicate a clock signal and to provide a drive current that is received over the clock channel and is used in generating the harvested voltage, and the value of the drive current being a function of the cascode drive voltage, and
a power harvesting control circuit coupled to the clock channel to receive a bias current over the clock channel and operable in an active mode to generate the cascode drive voltage responsive to this bias current and operable in a power down mode to generate the cascode drive voltage having a value that ensures that the maximum tolerable junction voltage is not exceeded for transistors in the clock and data channels, wherein the power harvesting control circuit comprises:
a first transistor having first and second signal nodes and a control node, the first signal node coupled to a first complementary clock line of the clock channel and the control node receiving the cascode drive voltage;
a second transistor having first and second signal nodes and a control node, the first signal node coupled to a second complementary clock line of the clock channel and the control node receiving the cascode drive voltage;
a third transistor having a first signal node coupled to the second signal node of the first transistor and having a second signal node coupled to a bias node, and having a control node adapted to receive a first complementary clock signal;
a fourth transistor having a first signal node coupled to the second signal node of the second transistor and having a second signal node coupled to the bias node, and having a control node adapted to receive a second complementary clock signal;
an external resistor coupled between the bias node and a reference voltage source;
wherein a bias current of the clock channel is operable to flow from the corresponding complementary clock line through the corresponding first or second transistor and through the activated one of the third and fourth transistors to the bias node and through the external resistor to generate a control voltage; and
a cascode drive voltage generation circuit coupled to the bias node and operable to generate the cascode drive voltage responsive to the control voltage during an active mode of operation and operable during a power down mode of operation to generate the cascode drive voltage having a value that is a function of a pull-up voltage applied on the complementary clock lines and of the harvested voltage.

2. The open drain transmitter of claim 1 , wherein each data channel comprises:
a first transistor having first and second signal nodes and a control node, the first signal node coupled to a first complementary data line of the data channel and the control node receiving the cascode drive voltage;
a second transistor having first and second signal nodes and a control node, the first signal node coupled to a second complementary data line of the data channel and the control node receiving the cascode drive voltage;
a third transistor having a first signal node coupled to the second signal node of the first transistor and having a second signal node coupled to the harvested node, and having a control node adapted to receive a first complementary data signal;
a fourth transistor having a first signal node coupled to the second signal node of the second transistor and having a second signal node coupled to the harvested node, and having a control node adapted to receive a second complementary data signal; and
wherein the drive current of the data channel is operable to flow from the corresponding complementary data line through the corresponding first or second transistor and through the activated one of the third and fourth transistors to the harvested node.

3. The open drain transmitter of claim 1 , wherein the communications and power harvesting circuit comprises:
a first transistor having first and second signal nodes and a control node, the first signal node coupled to a first complementary clock line of the clock channel and the control node receiving the cascode drive voltage;
a second transistor having first and second signal nodes and a control node, the first signal node coupled to a second complementary clock line of the clock channel and the control node receiving the cascode drive voltage;
a third transistor having a first signal node coupled to the second signal node of the first transistor and having a second signal node coupled to the harvested node, and having a control node adapted to receive a first complementary clock signal;
a fourth transistor having a first signal node coupled to the second signal node of the second transistor and having a second signal node coupled to the harvested node, and having a control node adapted to receive a second complementary clock signal; and
wherein the drive current of the clock channel is operable to flow from the corresponding complementary clock line through the corresponding first or second transistor and through the activated one of the third and fourth transistors to the harvested node.

4. The open drain transmitter of claim 1 , wherein the cascode drive voltage generation circuit comprises:
an operational amplifier having an inverting input coupled to receive the control voltage and a non-inverting input coupled to the harvested node to receive the harvested voltage, and having an output;
a transistor having a control node coupled to the output of the operational amplifier and having a first signal node coupled to the harvested node and a second signal node;
a first electronic device having a first node coupled to the second signal node of the transistor and a second node coupled to a bias node on which the cascode drive voltage is generated;
a second electronic device having a first node coupled to the bias node and a second node coupled to another node;
a first resistor coupled between the first complementary clock line and the another node; and
a second resistor coupled between the second complementary clock line and the another node.

5. The open drain transmitter of claim 1 further comprising a supplemental power feed circuit coupled to the node, the supplemental power feed circuit operable to supply a feed current to the node when the drive currents from the data and clock channels are insufficient to maintain the harvested voltage at the required value and power components in the transmitter, and operable to remove a shunt current from the node when drive currents are greater than the current needed to maintain the harvested voltage and power the components in the transmitter.

6. The open drain transmitter of claim 2 , wherein each data channel further comprises:
a first predriver circuit through which the first complementary data signal is applied to the control node of the third transistor;
a second predriver circuit through which the second complementary data signal is applied to the control node of the fourth transistor; and
a data serializer circuit coupled to the first and second predriver circuits and adapted to receive parallel input data, the serializer circuit operable to convert the received parallel input data into a corresponding serial data stream with each bit in this serial data stream being represented through the first and second complementary data signals.

7. The open drain transmitter of clai

Assignees

• St Microelectronics Int Nv

Inventors

• Gupta Nitin
• Sahni Paramjeet Singh
• Nandy Tapas
• Garg Manish

Classifications

• H03K3/01 Primary

  Details · CPC title

• H03K19/018528

  with at least one differential stage · CPC title

• H04N5/63 Primary

  Generation or supply of power specially adapted for television receivers · CPC title

• H04N5/44

  Receiver circuitry {for the reception of television signals according to analogue transmission standards} (H04N5/14 takes precedence) · CPC title