Amplifier

Patent metadata

Field	Value
Publication number	US-9331640-B2
Application number	US-201514604029-A
Country	US
Kind code	B2
Filing date	Jan 23, 2015
Priority date	Jan 24, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

An amplifier includes: a package which includes a pair of edge portions; an input terminal which is provided in the edge portion; output terminals which are provided in the edge portion; a first-stage FET chip which includes an input port directly connected to the input terminal by a bonding wire; a first-stage terminal which is provided in the edge portion and is directly connected to an output port of the first-stage FET chip by a bonding wire; a second-stage terminal which is provided in the edge portion; a second-stage FET chip which includes an output port directly connected to output terminals and by a bonding wire; and an impedance matching capacitor element of which one electrode is connected to the second-stage terminal and the input port of the second-stage FET chip.

First claim

What is claimed is:

1. An amplifier comprising:
a package which includes a first edge and a second edge, the first edge and the second edge are arranged in parallel to both sides of the package;
an input terminal which is provided in the first edge;
an output terminal which is provided in the second edge;
a first-stage amplifier chip which is provided in the package and includes an input port connected to the input terminal by a first bonding wire;
a first-stage terminal which is provided in the first edge and is connected to an output port of the first-stage amplifier chip by a second bonding wire;
a second-stage terminal which is provided in the first edge;
a second-stage amplifier chip which is provided in the package, includes an output port connected to the output terminal by a third bonding wire; and
an capacitor element which is provided in the package and of which one electrode is connected to the second-stage terminal through a fourth bonding wire and is connected to an input port of the second-stage amplifier chip through a fifth bonding wire,
wherein the distance between the first edge and the first-stage amplifier chip is shorter than the distance between the second edge and the first-stage amplifier chip, and
wherein the distance between the second edge and the second-stage amplifier chip is shorter than the distance between the first edge and the second-stage amplifier chip.

2. The amplifier of claim 1 ,
wherein the sum of the length of the fourth bonding wire and the length of the fifth bonding wire is longer than the length of the third bonding wire.

3. The amplifier of claim 1 ,
wherein the impedance of the input port of the first-stage amplifier chip is larger than the impedance of the input port of the second-stage amplifier chip, and the impedance of the output port of the first-stage amplifier chip is larger than the impedance of the output port of the second-stage amplifier chip.

4. The amplifier of claims 1 ,
wherein the width of the output terminal is larger than the width of each of the input terminal, the first-stage terminal, and the second-stage terminal.

5. The amplifier of claims 1 ,
further comprising a third terminal which is provided in the first edge and is located between the input terminal and the first-stage terminal,
wherein the third terminal connected to a ground potential.

6. The amplifier of claims 1 ,
wherein the first-stage terminal and the second-stage terminal are connected to each other at the outside of the package.

7. The amplifier of claims 1 ,
wherein the chip size of the second-stage FET chip is larger than that of the first-stage FET chip.

8. The amplifier of claim 1 ,
wherein the package is sealed by a resin.

9. The amplifier of claim 1 ,
wherein a matching circuit is not provided between the input terminal and the first-stage FET chip and between the output terminal and the second-stage FET chip.

10. The amplifier of claim 1 ,
wherein in the output power of the second-stage amplifier chip is larger than output power of the first-stage amplifier chip.

11. The amplifier of claim 10 ,
wherein a driving voltage of the first-stage amplifier chip is equal to a driving voltage of the second-stage amplifier chip.

12. The amplifier of claim 1 ,
wherein the first-stage amplifier chip and the second-stage amplifier chip are formed as discrete chips.

13. The amplifier of claim 1 ,
wherein the first-stage amplifier chip and the second-stage amplifier chip are composed of gallium nitride based material.

Assignees

• Sedi Inc

Inventors

• Miyazawa Naoyuki

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title