Multi-level inverter

Patent metadata

Field	Value
Publication number	US-9331595-B2
Application number	US-201414302121-A
Country	US
Kind code	B2
Filing date	Jun 11, 2014
Priority date	Jun 17, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A multi-level inverter includes: a rectifying unit to rectify received a three-phase voltage; a smoothing unit to receive the rectified voltage and provide the rectified voltage as voltages having different levels to first to third different nodes; and an inverter unit including a plurality of switch units to transfer the voltages having three levels provided from the smoothing unit, wherein the inverter unit includes a first switch unit provided between the first node and a first output terminal, a second switch unit provided between the second node and the first output terminal, a third switch unit provided between the third node and the first output terminal, a fourth switch unit provided between the first node and a second output terminal, a fifth switch unit provided between the second node and the second output terminal, and a sixth switch unit provided between the third node and the second output terminal.

First claim

What is claimed is:

1. A multi-level inverter comprising:
a rectifying unit configured to receive a phase voltage from a 3-phase power source and provide a rectified voltage;
a smoothing unit configured to receive the rectified voltage and provide the received rectified voltage as voltages having different levels to first to third nodes; and
an inverter unit including a plurality of switch units to transmit the voltages having three levels provided from the smoothing unit to a load,
wherein the inverter unit includes a first switch unit provided between the first node and a first output terminal, second switch units provided between the second node and the first output terminal, a third switch unit provided between the third node and the first output terminal, a fourth switch unit provided between the first node and a second output terminal, a fifth switch unit provided between the second node and the second output terminal, and a sixth switch unit provided between the third node and the second output terminal;
wherein the first switch unit comprises:
a first diode having directivity of a current from the first output terminal to the first node; and
a first power semiconductor having a current flow in the opposite direction of the first diode and connecting one side and the other side of the first diode,

wherein the third switch unit comprises:
a second diode having directivity of a current from the third node to the first output terminal; and
a second power semiconductor having a current flow in the opposite direction of the second diode and connecting one side and the other side of the second diode,

wherein the fifth switch unit comprises:
a first diode having directivity of a current from the second node to the second output terminal;
a first power semiconductor having a current flow in the opposite direction of the first diode and connecting one side and the other side of the first diode;
a second diode having a current flow in the opposite direction of the first diode and connected to the first diode in series; and
a second power semiconductor having a current flow in the opposite direction of the first power semiconductor and connecting one side and the other side of the second diode, and

wherein the cathode of the first diode and the cathode of the second diode in the fifth switch unit are directly connected to each other.

2. The multi-level inverter of claim 1 , wherein the first to sixth switch units include a power semiconductor and a diode.

3. The multi-level inverter of claim 1 , wherein the second switch units comprises:
a first diode having directivity of a current from the second node to the first output terminal;
a first power semiconductor having a current flow in the opposite direction of the first diode and connecting one side and the other side of the first diode;
a second diode having a current flow in the opposite direction of the first diode and connected to the first diode in series; and
a second power semiconductor having a current flow in the opposite direction of the first power semiconductor and connecting one side and the other side of the second diode.

4. The multi-level inverter of claim 1 , wherein the fourth switch unit comprises:
a first diode having directivity of a current from the second output terminal to the first node; and
a first power semiconductor having a current flow in the opposite direction of the first diode and connecting one side and the other side of the first diode.

5. The multi-level inverter of claim 4 , wherein the sixth switch unit comprises:
a second diode having directivity of a current from the third node to the second output terminal; and
a second power semiconductor having a current flow in the opposite direction of the second diode and connecting one side and the other side of the second diode.

6. The multi-level inverter of claim 1 , wherein the smoothing unit comprises:
first and second capacitors connected in series, wherein the first and second capacitors receive the rectified voltage through one side and the other side thereof, and one side, a common node, and the other side of the first and second capacitors are the first to third nodes.

7. The multi-level inverter of claim 6 , wherein the rectifying unit comprises:
first and second diodes connecting one side and the other side of each of the first and second capacitors and receiving a first phase voltage by the common node;
third and fourth diodes connecting one side and the other side of each the first and second capacitors and receiving a second phase voltage by the common node; and
fifth and sixth diodes connecting one side and the other side of each of the first and second capacitors and receiving a third phase voltage by the common node.

8. The multi-level inverter of claim 1 , further comprising: a plurality of unit power cells each including the rectifying unit, the smoothing unit, and the inverter unit, and further comprising a phase shift transformer receiving a phase voltage and providing a power signal having a predetermined phase to the unit power cells.

Assignees

• Lsis Co Ltd

Inventors

• Yoo Anno

Classifications

• H02M5/458 Primary

  using semiconductor devices only · CPC title

• H02M7/49

  Combination of the output voltage waveforms of a plurality of converters · CPC title

• H02M7/487

  Neutral point clamped inverters · CPC title

• H02M7/483

  Converters with outputs that each can have more than two voltages levels · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title