Switch mode power supply, control circuit and associated control method

Patent metadata

Field	Value
Publication number	US-9331583-B2
Application number	US-201314139601-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 24, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A switch mode power supply having an output terminal configured to provide an output voltage, the switch mode power supply has a first switch and a control circuit. The control circuit is configured to provide a switching control signal to control the first switch. The control circuit is configured to provide the switching control signal based on a first pulse signal having a first frequency and a second frequency for a light load condition, and the control circuit is configured to provide the switching control signal based on a second pulse signal for a non-light load condition.

First claim

We claim:

1. A control circuit for controlling a switch mode power supply, the switch mode power supply having an output terminal configured to provide an output voltage and having a first switch with a control terminal, wherein the control circuit comprising:
a mode management unit, having an input terminal and an output terminal, wherein the output terminal of the mode management unit is configured to provide a mode control signal;
a skip cycle mode control unit, having an input terminal and an output terminal, wherein the input terminal of the skip cycle mode control unit is configured to receive a feedback signal representing the output voltage, wherein the output terminal of the skip cycle mode control unit is configured to provide a first pulse signal having a first frequency and a second frequency, wherein the first frequency and the second frequency are predetermined;
a normal mode control unit, having an output terminal configured to provide a second pulse signal; and
a drive signal management unit, having a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal of the drive signal management unit is coupled to the output terminal of the mode management unit, the second input terminal of the drive signal management unit is coupled to the output terminal of the skip cycle mode control unit, the third input terminal of the drive signal management unit is coupled to the output terminal of the normal mode control unit, and the output terminal of the drive signal management unit is configured to provide a switching control signal to the control terminal of the first switch based on the first pulse signal, the second pulse signal and the mode control signal; wherein
the input terminal of the mode management unit is configured to receive the switching control signal, and the output terminal of the mode management unit is configured to provide the mode control signal via comparing a frequency of the switching control signal with a frequency threshold.

2. The control circuit of claim 1 , wherein the drive signal management unit is configured to provide the switching control signal based on the first pulse signal when the mode control signal is in a first state, and the drive signal management unit is configured to provide the switching control signal based on the second pulse signal when the mode control signal is in a second state.

3. The control circuit of claim 1 , wherein the skip cycle mode control unit is configured to provide the first pulse signal based on a low-frequency pulse signal, wherein a duty cycle of the low-frequency pulse signal is adjusted with the feedback signal.

4. The control circuit of claim 1 , wherein the skip cycle mode control unit further comprising:
a low-frequency pulse generator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the low-frequency pulse generator is configured to receive the feedback signal, the second input terminal of the low-frequency pulse generator is configured to receive a modulation signal, and the output terminal of the low-frequency pulse generator is configured to provide a low-frequency pulse signal via comparing the feedback signal with the modulation signal, and wherein the low-frequency pulse signal is in a first state when the feedback signal is larger than the modulation signal, and the low-frequency pulse signal is in a second state when the feedback signal is less than the modulation signal; and
a mix-frequency pulse generator, having an input terminal and an output terminal, wherein the input terminal of the mix-frequency pulse generator is coupled to the output terminal of the low-frequency pulse generator, and the output terminal of the mix-frequency pulse generator is configured to provide the first pulse signal based on the low-frequency pulse signal, and wherein the first pulse signal keeps ineffective when the low-frequency pulse signal is in the first state, and the first pulse signal comprises effective pulses having the second frequency when the low-frequency pulse signal is in the second state.

5. The control circuit of claim 4 , wherein the mix-frequency pulse generator further comprising:
a first capacitor, having a first terminal and a second terminal;
an OR gate, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the OR gate is configured to receive the low-frequency pulse signal, the second input terminal of the OR gate is configured to receive the first pulse signal;
a first controlling switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first controlling switch is coupled to the first terminal of the first capacitor, the second terminal of the first controlling switch is coupled to the second terminal of the first capacitor, and the control terminal of the first controlling switch is coupled to the output terminal of the OR gate;
a first current source, configured to charge the first capacitor; and
a first comparator, configured to provide the first pulse signal via comparing a voltage across the first capacitor with a reference signal.

6. The control circuit of claim 1 , wherein the first frequency is equal to or below a lower limiter of an audible frequency range, and the second frequency is equal to or above an upper limiter of the audible frequency range.

7. The control circuit of claim 1 , wherein the drive signal management unit is configured to turn OFF the first switch by the switching control signal when a current flowing through the first switch is larger than a peak current threshold.

8. The control circuit of claim 1 , wherein the normal mode control unit further comprising:
a second capacitor, having a first terminal and a second terminal;
a second current source, configured to charge the second capacitor;
a second controlling switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second controlling switch is coupled to the first terminal of the second capacitor, the second terminal of the second controlling switch is coupled to the second terminal of the second capacitor, and the control terminal of the second controlling switch is configured to receive the switching control signal; and
a second comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second comparator is coupled to the first terminal of the second capacitor, the second input terminal of the second comparator is configured to receive the feedback signal, and the output terminal is configured to provide the second pulse signal.

9. The control circuit of claim 1 , wherein the drive signal management unit further comprising:
a third comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the third comparator is configured to receive a current sense signal representing a current flowing through the first switch, the second input terminal of the third comparator is configured to receive a peak current threshold;
a first flip-flop, having a reset terminal, a set terminal, and an output terminal, wherein the reset terminal of the first flip-flop is coupled to the output terminal of the third comparator, the set terminal of the first flip-flop is coupled to the output terminal of the skip cycle mode control unit to receive the first pulse signal;
a second flip-flop, having a reset terminal, a set terminal, and an output terminal, wherein the reset terminal of the second flip-flop is coupled to the output terminal of the thir

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Zhang Junming
• Long Hao
• Li Hui

Classifications

• Y02B70/16

  Cross-Sectional Technologies · mapped topic

• H02M2001/0032

  Electricity · mapped topic

• H02M3/33507 Primary

  with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title

• H02M1/0032

  Control circuits allowing low power mode operation, e.g. in standby mode · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title