3-dimensional (3D) non-volatile memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9331272-B2
Application number	US-201214125198-A
Country	US
Kind code	B2
Filing date	Jun 11, 2012
Priority date	Jun 10, 2011
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Provided are 3D non-volatile memory devices and methods of fabricating the same. A 3D non-volatile memory device according to an embodiment of the present invention includes a plurality of conductive lines, which are separated from one another in parallel; a plurality of conductive planes, which extend across the plurality of conductive lines and are separated from one another in parallel; and non-volatile data storage layer patterns, which are respectively arranged at regions of intersection at which the plurality of conductive lines and the plurality of conductive planes cross each others.

First claim

What is claimed is:

1. A 3D non-volatile memory device comprising:
a plurality of conductive lines separated from one another in parallel;
a plurality of conductive planes extending across the plurality of conductive lines and are separated from one another in parallel;
non-volatile data storage layer patterns, each arranged at regions of intersection at which the plurality of conductive lines and the plurality of conductive planes cross each others; and
selection diode layer patterns connected to the non-volatile data storage layer pattern in series by stacking the selection diode layer pattern and the non-volatile data storage layer pattern on each other, between the regions of intersection,
wherein at least one of the non-volatile data storage layer patterns and the selection diode layer patterns surround the plurality of conductive lines.

2. The 3D non-volatile memory device of claim 1 , wherein the non-volatile data storage layer pattern comprises a phase change material, a variable resistive material, a programmable metallization cell (PMC), a magnetic material, or a combination thereof.

3. The 3D non-volatile memory device of claim 1 , further comprising insertion electrode layers between the non-volatile data storage layer patterns and the selection diode layer patterns.

4. A 3D non-volatile memory device comprising:
a plurality of conductive lines, which include linear patterns that extend on a substrate in a first direction parallel to the main surface of the substrate and are 3-dimensionally arranged by being arranged in parallel with one another and separated from one another in a second direction and a third direction different from the first direction;
a plurality of conductive planes, which extend on the substrate in the second direction and the third direction, are separated from one another in parallel in the first direction, and cross the plurality of conductive lines;
insulation layer patterns, which are arranged between the plurality of conductive planes;
non-volatile data storage layer patterns, which are respectively arranged at regions of intersection at which the plurality of conductive lines and the plurality of conductive planes cross each others; and
selection diode layer patterns connected to the non-volatile data storage layer pattern in series by stacking the selection diode layer pattern and the non-volatile data storage layer pattern on each other, between the regions of intersection,
wherein at least one of the non-volatile data storage layer patterns and the selection diode layer patterns surround the plurality of conductive lines.

5. The 3D non-volatile memory device of claim 4 , wherein the non-volatile data storage layer pattern comprises a phase change material, a variable resistive material, a programmable metallization cell (PMC), a magnetic material, or a combination thereof.

6. The 3D non-volatile memory device of claim 4 , further comprising supporting structures, wherein each supporting structure penetrates insulation layer patterns and then also penetrates the plurality of conductive lines.

7. A method of fabricating a 3D non-volatile memory device, the method comprising:
forming a plurality of conductive lines, which are separated from one another in parallel;
forming a plurality of non-volatile data storage layer patterns on the plurality of conductive lines;
forming a plurality of conductive planes, which extend across the plurality of conductive lines and are separated from one another in parallel, such that regions of intersection, at which the plurality of conductive lines and the plurality of conductive planes cross each other, are defined on the non-volatile data storage layer patterns; and
forming selection diode layer patterns connected to the non-volatile data storage layer pattern in series by stacking the selection diode layer pattern and the non-volatile data storage layer pattern on each other, between the regions of intersection,
wherein at least one of the non-volatile data storage layer patterns and the selection diode layer patterns surround the plurality of conductive lines.

8. The method of claim 7 , wherein the forming of the non-volatile data storage layer patterns comprises:
forming non-volatile data storage layers on the plurality of conductive lines; and
forming the non-volatile data storage layer patterns by patterning the non-volatile data storage layers at a constant interval.

9. The method of claim 7 , wherein the non-volatile data storage layer pattern comprises a phase change material, a variable resistive material, a programmable metallization cell (PMC), a magnetic material, or a combination thereof.

Assignees

• Hwang Cheol Seong
• Seok Jun Yeong
• Univ Seoul Nat R & Db Found

Inventors

• Hwang Cheol Seong
• Seok Jun Yeong

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H01L45/04

  Electricity · mapped topic

• H01L45/122

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic