Replacement gate structure on FinFET devices with reduced size fin in the channel region

Patent metadata

Field	Value
Publication number	US-9331202-B2
Application number	US-201514731876-A
Country	US
Kind code	B2
Filing date	Jun 5, 2015
Priority date	Jun 16, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

First claim

What is claimed:

1. A FinFET device comprising a channel region, a plurality of source/drain regions, a gate width and a gate length, the device further comprising:
a fin defined in a semiconductor substrate, said fin extending across said source/drain regions and said channel region in said gate length direction, wherein said fin, when viewed from above, comprises a reduced-size channel portion that is positioned between source/drain portions of said fin, said source/drain portions of said fin having a first width in said gate width direction, said reduced-size channel portion of said fin having a second width in said gate width direction, wherein said second width is less than said first width;
and wherein, when viewed in a cross-section taken along an entire axial length of said fin through said reduced-size channel portion and said source/drain portions of said fin, said source/drain portion of said fin have a first vertical height and said reduced-size channel portion of said fin has a second vertical height, wherein said second vertical height is less than said first vertical height; and
a gate electrode positioned above and around at least a portion of said reduced-size channel portion of said fin.

2. The device of claim 1 , wherein said gate electrode is positioned above and around an entire axial length of said reduced-size channel portion.

3. The device of claim 1 , further comprising a sidewall spacer that is positioned around said gate electrode and vertically above a portion of said source/drain portions of said fin.

4. The device of claim 2 , wherein said gate electrode is comprised of at least one layer of metal.

5. The device of claim 4 , further comprising a high-k gate insulation layer positioned between said gate electrode and said reduced-size channel portion of said fin.

6. The device of claim 1 , wherein said second width of said reduced-size channel portion is about 40-60% less than said first width of said source/drain portions of said fin.

7. The device of claim 1 , wherein said second width of said reduced-size channel portion is substantially uniform along its entire axial length in said gate length direction.

8. The device of claim 7 , wherein said first width of said source/drain portions of said fin is substantially uniform along their entire axial length in said gate length direction.

9. The device of claim 1 , wherein said second vertical height of said reduced-size channel portion is about 0.5-5 nm less than said first vertical height of said source/drain portions of said fin.

10. A FinFET device comprising a channel region, a plurality of source/drain regions, a gate width and a gate length, the device further comprising:
a fin defined in a semiconductor substrate, said fin extending across said source/drain regions and said channel region in said gate length direction, wherein:
said fin, when viewed from above, comprises a reduced-size channel portion that is positioned between source/drain portions of said fin, said source/drain portions of said fin having a first width in said gate width direction, said reduced-size channel portion of said fin having a second width in said gate width direction, wherein said second width is less than said first width, wherein said second width of said reduced-size channel portion is about 40-60% less than said first width of said source/drain portions of said fin; and
when viewed in a cross-section taken along an entire axial length of said fin through said reduced-size channel portion and said source/drain portions of said fin, said source/drain portions of said fin have a first vertical height and said reduced-size channel portion of said fin has a second vertical height, wherein said second vertical height is less than said first vertical height; and
a gate electrode positioned above and around at least a portion of said reduced-size channel portion of the fin.

11. The device of claim 10 , wherein said gate electrode is positioned above and around an entire axial length of said reduced-size channel portion.

12. The device of claim 10 , further comprising a sidewall spacer that is positioned around said gate electrode and vertically above a portion of said source/drain portions of said fin.

13. The device of claim 10 , wherein said second width of said reduced-size channel portion is substantially uniform along its entire axial length in said gate length direction.

14. The device of claim 13 , wherein said first width of said source/drain portions of said fin is substantially uniform along their entire axial length in said gate length direction.

15. The device of claim 10 , wherein said second vertical height of said reduced-size channel portion is about 0.5-5 nm less than said first vertical height of said source/drain portions of said fin.

16. A FinFET device comprising a channel region, a plurality of source/drain regions, a gate width and a gate length, the device further comprising:
a fin defined in a semiconductor substrate, said fin extending across said source/drain regions and said channel region in said gate length direction, wherein said fin, when viewed from above, comprises a reduced-size channel portion that is positioned between source/drain portions of said fin, and when viewed in a cross-section taken along an entire axial length of said fin through said reduced-size channel portion and said source/drain portions of said fin, said source/drain portions of said fin have a first vertical height and said reduced-size channel portion of said fin has a second vertical height, wherein said second vertical height of said reduced-size channel portion is about 0.5-5 nm less than said first vertical height of said source/drain portions of said fin; and
a gate electrode positioned above and around at least a portion of said reduced-size channel portion of said fin.

17. The device of claim 16 , wherein said gate electrode is positioned above and around an entire axial length of said reduced-size channel portion.

18. The device of claim 16 , further comprising a sidewall spacer that is positioned around said gate electrode and vertically above a portion of said source/drain portions of said fin.

19. The device of claim 16 , wherein, when viewed from above, said source/drain portions of said fin have a first width in said gate width direction and said reduced-size channel portion of said fin has a second width in said gate width direction, wherein said second width is less than said first width.

20. The device of claim 19 , wherein said second width of said reduced-size channel portion is about 40-60% less than said first width of said source/drain portions of said fin.

21. The device of claim 20 , wherein said second width of said reduced-size channel portion is substantially uniform along its entire axial length in said gate length direction.

22. The device of claim 21 , wherein said first width of said source/drain portions of said fin is substantially uniform along their entire axial length in said gate length direction.

Assignees

• Globalfoundries Inc

Inventors

• Liu Bingwu
• Zang Hui

Classifications

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title