Air gap formation between bit lines with top protection

Patent metadata

Field	Value
Publication number	US-9330969-B2
Application number	US-201414340998-A
Country	US
Kind code	B2
Filing date	Jul 25, 2014
Priority date	Feb 12, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.

First claim

It is claimed:

1. A method of forming bit lines of a nonvolatile memory comprising:
forming a sacrificial layer of a sacrificial material above a memory array;
subsequently forming a plurality of elongated openings in the sacrificial layer;
subsequently forming a plurality of bit lines in the plurality of elongated openings;
subsequently selectively forming a protective material on exposed upper surfaces of the plurality of bit lines while leaving upper surfaces of sacrificial material portions exposed between bit lines; and
subsequently performing anisotropic etching of the sacrificial material portions to form air gaps between bit lines, the protective material remaining in place to mask upper surfaces of the plurality of bit lines throughout the etching of the sacrificial material portions, wherein the anisotropic etching leaves residual sacrificial material along sides of the bit lines.

2. The method of claim 1 wherein the sacrificial material portions are etched by a selective dry etch that etches the sacrificial material at a higher rate than the protective material.

3. The method of claim 1 wherein the sacrificial material comprises:
undoped silicon dioxide, fluorine doped silicon oxide, carbon doped silicon oxide, hydrogen doped silicon oxide, porous silicon dioxide, silicon nitride, silicon oxynitride, a polymer, or silicon.

4. The method of claim 1 wherein the protective material is a metal silicide that is formed by silicidation of bit line metal.

5. The method of claim 4 wherein the protective material is copper silicide that is formed by silicidation of bit line copper, or the protective material is tungsten silicide that is formed by silicidation of bit line tungsten.

6. The method of claim 1 wherein the protective material comprises tungsten that is deposited by selective Chemical Vapor Deposition (CVD) that provides substantially no tungsten deposition on the upper surfaces of the sacrificial material portions.

7. The method of claim 6 wherein the tungsten that is deposited by selective CVD acts as a nucleation layer for subsequent deposition of additional tungsten by electroless plating.

8. The method of claim 1 wherein the protective material is cobalt tungsten phosphide that is selectively formed on copper.

9. The method of claim 1 further comprising: prior to forming the plurality of bit lines in the plurality of elongated openings, oxidizing exposed surfaces of the sacrificial layer to form oxide portions along sides of bit lines, and etching the sacrificial material portions using an etch that selectively etches the sacrificial material at a higher rate than the oxide portions so that substantially all of the sacrificial material is removed while the oxide portions remain.

10. A method of forming bit lines of a nonvolatile memory comprising:
forming a sacrificial layer of a sacrificial material above a memory array;
subsequently forming a plurality of elongated openings in the sacrificial layer;
subsequently forming a plurality of bit lines in the plurality of elongated openings;
subsequently selectively forming a protective material on exposed upper surfaces of the plurality of bit lines while leaving upper surfaces of sacrificial material portions exposed between bit lines, the protective material deposited by Chemical Vapor Deposition (CVD) of a tungsten nucleation layer that provides substantially no tungsten deposition on the upper surfaces of the sacrificial material portions, and subsequent deposition of an additional tungsten layer on the tungsten nucleation layer by electroless plating; and
subsequently etching the sacrificial material portions to form air gaps between bit lines, the protective material remaining in place throughout the etching of the sacrificial material portions.

11. The method of claim 10 wherein the sacrificial material portions are etched by a selective dry etch that etches the sacrificial material at a higher rate than the protective material.

12. The method of claim 10 wherein the sacrificial material portions are etched by anisotropic etching while the protective material masks the upper surfaces of the plurality of bit lines.

13. The method of claim 12 wherein the anisotropic etching leaves residual sacrificial material along sides of the bit lines.

14. The method of claim 10 wherein the sacrificial material comprises:
undoped silicon dioxide, fluorine doped silicon oxide, carbon doped silicon oxide, hydrogen doped silicon oxide, porous silicon dioxide, silicon nitride, silicon oxynitride, a polymer, or silicon.

15. The method of claim 10 further comprising: prior to forming the plurality of bit lines in the plurality of elongated openings, oxidizing exposed surfaces of the sacrificial layer to form oxide portions along sides of bit lines, and etching the sacrificial material portions using an etch that selectively etches the sacrificial material at a higher rate than the oxide portions so that substantially all of the sacrificial material is removed while the oxide portions remain.

Assignees

• Sandisk Technologies Inc

Inventors

• Sel Jong Sun
• Gunji-Yoneoka Marika
• Takeguchi Naoki
• Park Chan
• Pham Tuan D
• Tokunaga Kazuya

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title