Methods of forming semiconductor devices

Patent metadata

Field	Value
Publication number	US-9330966-B2
Application number	US-201113313172-A
Country	US
Kind code	B2
Filing date	Dec 7, 2011
Priority date	Dec 27, 2010
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a plurality of conductive structures on a substrate;
forming a first insulation layer on the plurality of conductive structures, the first insulation layer extending in both a first direction that is parallel to a bottom surface of the substrate and a second direction that is parallel to the bottom surface of the substrate and that is perpendicular to the first direction;
patterning the first insulation layer to form a first insulation pattern that includes a hole that extends through the first insulation pattern in a third direction that is perpendicular to both the first direction and the second direction, the hole exposing the substrate;
forming a sacrificial pattern in the hole, the sacrificial pattern comprising a spin-on hard mask layer including carbon (C);
forming a second insulation pattern on the first insulation pattern and on the sacrificial pattern, the second insulation pattern including a trench therein that extends in the first direction and that extends through the second insulation pattern in the third direction to expose a surface of the sacrificial pattern; and then
removing the sacrificial pattern from the first insulation pattern;
forming a spacer on sidewalls of the hole and the trench; and
forming a wiring structure between opposing sidewalls of the spacer in the hole and the trench,
wherein a width of the trench in the second direction is equal to a width of the hole in the second direction.

2. The method of claim 1 , wherein:
removing the sacrificial pattern from the first insulation pattern exposes a surface of a drain electrode; and
the wiring structure directly contacts the drain electrode.

3. The method of claim 1 , wherein forming the sacrificial pattern includes:
forming a sacrificial layer on the first insulation pattern to substantially fill the hole; and
removing an upper portion of the sacrificial layer by performing a planarization process until an upper surface of the first insulation pattern is exposed.

4. The method of claim 1 ,
wherein the wiring structure comprises an interconnection in the hole and a conductive line in the trench, and
wherein forming the wiring structure comprises forming the interconnection and the conductive line by a same process.

5. A method of forming a semiconductor device, comprising:
forming a first insulation pattern on a substrate to cover a plurality of conductive structures thereon, the first insulation pattern including a penetration-hole therein through which a contact area of the substrate is exposed;
forming a sacrificial layer that comprises a spin-on hard mask layer including a carbon (C)-based material in the penetration-hole in the first insulation pattern;
removing an upper portion of the sacrificial layer by performing a planarization process until an upper surface of the first insulation pattern is exposed to convert the sacrificial layer into a sacrificial pattern;
forming a second insulation pattern on the first insulation pattern, the second insulation pattern including a trench therein that is connected with the penetration-hole and shaped into a line;
removing the sacrificial pattern from the penetration-hole to connect the trench with the penetration-hole and expose the contact area; and then
forming a spacer on sidewalls of the penetration-hole and the trench; and
forming a wiring structure in the penetration-hole and the trench, the wiring structure including an interconnection in the penetration-hole that directly contacts the contact area of the substrate and a conductive line that fills the trench in the first direction and is integrally connected to the interconnection in a body.

6. The method of claim 5 , wherein the first insulation pattern extends in both a first direction that is parallel to a bottom surface of the substrate and a second direction that is parallel to the bottom surface of the substrate and that is perpendicular to the first direction, wherein the penetration-hole extends in a third direction that is perpendicular to both the first direction and the second direction, wherein the trench extends in the first direction, and wherein a width of the trench in the second direction is equal to a width of the penetration-hole in the second direction.

7. The method of claim 6 , wherein the spacer is formed by forming a spacer layer using an atomic layer deposition (ALD) process and then etching the spacer layer.

Assignees

• Kim Sun-Young
• Song Jun-Eui
• Lim Tae-Wan
• Samsung Electronics Co Ltd

Inventors

• Kim Sun-Young
• Song Jun-Eui
• Lim Tae-Wan

Classifications

• H10W20/0886

  involving forming a via in a via-level dielectric prior to deposition of a trench-level dielectric · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/084 Primary

  for dual-damascene structures · CPC title

• H01L21/76831

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic