Semiconductor devices including capacitors

Patent metadata

Field	Value
Publication number	US-9330960-B2
Application number	US-201414296850-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jun 10, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first capacitor structure including a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate;
a second capacitor structure including a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, the second capacitor structure being adjacent to the first capacitor structure;
an insulation pattern partially filling a space between the first and second capacitor structures, an air gap being formed between the first and second capacitor structures on the insulation pattern; and
a plate electrode overlying the insulation pattern and contacting the first and second upper electrodes, a boundary of the air gap being defined by the plate electrode.

2. The semiconductor device of claim 1 , wherein the plate electrode includes at least one plate electrode layer.

3. The semiconductor device of claim 1 , wherein the first and second upper electrodes are spaced apart from each other.

4. The semiconductor device of claim 1 , wherein the first and second capacitor structures have substantially the same shape,
and wherein each of a first stacked structure including the first lower electrode and the first dielectric layer and a second stacked structure including the second lower electrode and the second dielectric layer has a cylindrical shape, and the first and second upper electrodes fill inner spaces of the cylindrical first and second stacked structures, respectively.

5. The semiconductor device of claim 4 , wherein upper portions of the first upper electrode and the first dielectric layer protrude from a top surface of the first lower electrode, and upper portions of the second upper electrode and the second dielectric layer protrude from a top surface of the second lower electrode.

6. The semiconductor device of claim 4 , wherein an upper width of each of the first and second capacitor structures is greater than a distance between the first and second capacitor structures.

7. The semiconductor device of claim 6 , wherein the upper width of each of the first and second capacitor structures is about two times to about 10 times of the distance between the first and second capacitor structures.

8. The semiconductor device of claim 4 , wherein each of the first and second lower electrodes has a cylindrical shape of which an inner diameter becomes narrower from a top portion toward a bottom portion thereof, the top portion being more distant from the substrate than the bottom portion.

9. The semiconductor device of claim 1 , wherein the insulation pattern includes an insulating material having a dielectric constant lower than that of silicon nitride.

10. The semiconductor device of claim 1 , wherein the insulation pattern fills a lower portion of the space between the first and second capacitor structures, and the insulation pattern has a thickness of about 50% to about 90% of a height of the first and second capacitor structures.

11. The semiconductor device of claim 1 , further comprising an insulation pattern having a top surface substantially coplanar with a top surface of the first and second capacitor structures.

12. A semiconductor device, comprising:
a first capacitor structure including a first lower electrode, a first dielectric layer and a first upper electrode, the first lower electrode having a cylindrical shape, the first dielectric layer contacting an inner wall of the cylindrical first lower electrode, and the first upper electrode being on the first dielectric layer and filling an inner space of the cylindrical first lower electrode;
a second capacitor structure including a second lower electrode, a second dielectric layer and a second upper electrode, the second lower electrode having a cylindrical shape, the second dielectric layer contacting an inner wall of the cylindrical second lower electrode, and the second upper electrode being on the second dielectric layer and filling an inner space of the cylindrical second lower electrode;
an insulation pattern partially filling a space between the first and second capacitor structures; and
a plate electrode overlying the insulation pattern and contacting the first and second upper electrodes, an air gap being formed under the plate electrode between the first and second capacitor structures on the insulation pattern.

13. The semiconductor device of claim 12 , wherein an upper width of each of the first and second capacitor structures is greater than a distance between the first and second capacitor structures.

14. The semiconductor device of claim 12 , wherein the insulation pattern fills a lower portion of the space between the first and second capacitor structures, and a top surface of the insulation pattern is about 50% to about 90% of a height of the first and second capacitor structures.

15. A semiconductor device, comprising:
a first capacitor structure on a substrate and having a first top portion and a first bottom portion, the first top portion being more distant from the substrate than the first bottom portion;
a second capacitor structure on the substrate and having a second top portion and a second bottom portion, the second top portion being more distant from the substrate than the second bottom portion;
an insulation pattern partially filling a space between the first and second capacitor structures, an air gap being formed between the first and second capacitor structures on the insulation pattern; and
a plate electrode overlying the insulation pattern and contacting the first and second upper electrodes, a boundary of the air gap being defined by the plate electrode;
wherein a distance d1 between the first top portion and the second top portion is less than a distance d2 between the first bottom portion and the second bottom portion.

16. The semiconductor device of claim 15 , wherein the insulation pattern fills a lower portion of the space between the first and second capacitor structures, and the insulation pattern has a thickness of about 50% to about 90% of a height of the first and second capacitor structures.

17. The semiconductor device of claim 15 , further comprising an insulation pattern having a top surface substantially coplanar with a top surface of the first and second capacitor structures.

Assignees

• Cho Young-Seung
• Kim Sung-Eui
• Kim Ji-Young
• Jeong Hoon
• Kim Chan-Won
• Seo Jong-Bom
• Lee Seung-Jun
• Lee Jun-Soo
• Samsung Electronics Co Ltd

Inventors

• Cho Young-Seung
• Kim Sung-Eui
• Kim Ji-Young
• Jeong Hoon
• Kim Chan-Won
• Seo Jong-Bom
• Lee Seung-Jun
• Lee Jun-Soo

Classifications

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10B12/312

  with a bit line higher than the capacitor · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title