Semiconductor structure and method for manufacturing semiconductor structure
US-12046478-B2 · Jul 23, 2024 · US
US9330910B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9330910-B2 |
| Application number | US-201113882631-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 31, 2011 |
| Priority date | Nov 1, 2010 |
| Publication date | May 3, 2016 |
| Grant date | May 3, 2016 |
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A method of forming an array of nanostructures includes forming a plurality of seed points on a surface of a substrate, and growing masks from the seed points to create masked regions of the substrate underlying the masks. A remainder of the substrate comprises an unmasked region. Each mask and masked region increase in size with growth time while the unmasked region of the substrate decreases in size. During the growing, the unmasked region is etched to remove material from the substrate in a depth direction, and, simultaneously, unetched structures are formed from the masked regions of the substrate underlying the masks. Each of the unetched structures has a lateral size that increases with depth.
Opening claim text (preview).
The invention claimed is: 1. A method of forming an array of nanostructures, the method comprising: forming a plurality of seed points on a surface of a substrate; growing masks from the seed points to create masked regions of the substrate underlying the masks, a remainder of the substrate comprising an unmasked region, each mask and masked region increasing in size with growth time while the unmasked region of the substrate decreases in size; during the growing, etching the unmasked region to remove material from the substrate in a depth direction, and during the etching, forming unetched structures from the masked regions of the substrate, each unetched structure having a lateral size that increases with depth. 2. The method of claim 1 , wherein the material is removed from the substrate at an etch rate of between about 110 nm/min and about 125 nm/min. 3. The method of claim 1 , wherein a base width of each unetched structure increases at a rate of between about 20 nm/min and about 60 nm/min during the etching, the base width corresponding to a maximum lateral size at a given etch depth. 4. The method of claim 1 , wherein the unetched structures include an oxide layer thereon. 5. The method of claim 1 , wherein the substrate comprises a semiconductor. 6. The method of claim 1 , wherein forming the seed points comprises reacting a first gas and a second gas with the surface of the substrate. 7. The method of claim 6 , wherein etching the unmasked regions of the substrate comprises plasma etching with the first gas, the first gas having a high selectivity of silicon to silicon oxide.
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