Semiconductor integrated circuit capable of performing self-test

Patent metadata

Field	Value
Publication number	US-9330788-B2
Application number	US-201414481161-A
Country	US
Kind code	B2
Filing date	Sep 9, 2014
Priority date	Mar 14, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

According to one embodiment, there is provided a semiconductor integrated circuit including a memory, a capture register, a writing unit, and a control unit. The memory includes a plurality of memory bit cells. The capture register stores data read out from a memory bit cell selected out of the plurality of memory bit cells. The writing unit writes relevant data according to the data stored in the capture register to the memory bit cell. The control unit reads the relevant data from the written memory bit cell, compares the relevant data according to the data stored in the capture register and the read-out relevant data, controls the capture register such that a comparison result is stored by overwriting a result as a self-test result about the written memory bit cell, and controls the writing unit such that the original data according to the read-out relevant data is rewritten to the selected memory bit cell.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a memory which includes a plurality of memory bit cells;
a self-test circuit which controls write operation and read operation to/from the memory, the self-test circuit being able to output an expectation value;
a capture register which, according to control state of the self-test circuit, stores data read out from a memory bit cell selected by the self-test circuit or comparison result that is obtained by comparing data read out from a memory bit cell selected by the self-test circuit with the expectation value output from the self-test circuit;
a writing unit which, according to control state of the self-test circuit, writes the data stored in the capture register or data processed from the stored data or data read out from a memory bit cell selected by the self-test circuit, to the memory bit cell; and
a control unit which, according to control state of the self-test circuit, generates the processed data to be written to the memory bit cell by the writing unit, outputs the processed data read out from the memory bit cell selected by the self-test circuit to the capture register, compares the processed data stored in the capture register and the processed data generated by the control unit, output a result of the comparison to the capture register to be overwritten as a self-test result about the memory bit cell, restores an original data from data read out from the memory bit cell selected by the self-test circuit, and outputs the restored original data to be rewritten to the memory bit cell selected by the self-test circuit.

2. The semiconductor integrated circuit according to claim 1 ,
wherein the control unit includes a generation unit which makes the data stored in the capture register logically inverted to generate inverted data,
wherein the writing unit writes the generated inverted data to the selected memory bit cell, and
wherein the control unit further includes
a comparator which compares the inverted data read out from the selected memory bit cell and the generated inverted data and outputs a comparison result as the self-test result about the selected memory bit cell to the capture register, and
a first switching unit which is switched between a first state of supplying the stored data to the generation unit and a second state of supplying the inverted data read out from the selected memory bit cell to the generation unit.

3. The semiconductor integrated circuit according to claim 2 ,
wherein the control unit further includes
a second switching unit which switches the operation of the capture register between a first mode of accumulating and storing a comparison result received from the comparator and a second mode of storing a comparison result received from the comparator without accumulating the comparison result, and
wherein the self-test circuit controls the second switching unit such that test data is supplied to the plurality of memory bit cells and the operation is switched to the first mode when a system to control the plurality of memory bit cells is powered up, and controls the second switching unit such that the test data is not supplied to the plurality of memory bit cells and the operation is switched to the second mode during a period when the system is operated.

4. The semiconductor integrated circuit according to claim 3 ,
wherein the second switching unit switches the operation of the capture register between the first mode and the second mode according to self-test signal which is supplied from the self-test circuit.

5. The semiconductor integrated circuit according to claim 4 ,
wherein the second switching unit switches the operation to the first mode when the self-test signal is at a non-active level, and switches the operation to the second mode when the self-test signal is at an active level.

6. The semiconductor integrated circuit according to claim 5 ,
wherein the second switching unit includes
a logical inversion operator which makes the self-test signal logically inverted, and
a logical multiplication operator which performs a logical multiplication operation between the logically-inverted self-test signal and the output of the capture register, and
wherein an output terminal of the logical multiplication operator is connected to an input of the capture register.

7. The semiconductor integrated circuit according to claim 3 ,
wherein the self-test circuit causes the first switching unit to be switched to the first state so that the comparator outputs the comparison result to the capture register during the operation of the system, and after the comparator completely outputs the comparison result to the capture register, causes the first switching unit to be switched to the second state so that the read-out data is rewritten to the selected memory bit cell.

8. The semiconductor integrated circuit according to claim 7 ,
wherein the first switching unit is switched between the first state and the second state according to a first select signal supplied from the self-test circuit.

9. The semiconductor integrated circuit according to claim 8 ,
wherein the first switching unit is switched to the first state when the first select signal is at a first level, and switched to the second state when the first select signal is at a second level.

10. The semiconductor integrated circuit according to claim 7 ,
wherein the first switching unit is switched to the first state, the second state, or a third state in which a fixed bit value “0” is supplied to the generation unit according to a first select signal supplied from the self-test circuit.

11. The semiconductor integrated circuit according to claim 10 ,
wherein the first switching unit is switched to the first state when the first select signal is at a first level, and switched to the second state when the first select signal is at a second level, and switched to the third state when the first select signal is at a third level.

12. The semiconductor integrated circuit according to claim 2 ,
wherein when the inverted data read out from the selected memory bit cell and the generated inverted data are matched with each other, the comparator outputs a comparison result which indicates “Pass”, and
wherein when the inverted data read out from the selected memory bit cell and the generated inverted data are not matched with each other, the comparator outputs a comparison result which indicates “Fail”.

13. A semiconductor integrated circuit comprising:
a memory which includes a plurality of memory bit cells;
a self-test circuit which controls write operation and read operation to/from the memory, the self-test circuit being able to output an expectation value;
a capture register which, according to control state of the self-test circuit, stores data read out from a memory bit cell selected by the self-test circuit or comparison result that is obtained by comparing data read out from a memory bit cell selected by the self-test circuit with the expectation value output from the self-test circuit;
a writing unit which, according to control state of the self-test circuit, writes the data stored in the capture register or data processed from the stored data or data read out from a memory bit cell selected by the self-test circuit, to the memory bit cell; and
a control unit which, according to control state of the self-test circuit, generates the processed data to be written to the memory bit cell by the writing unit, outputs the processed data read out from the memory bit cell selected by the self-test circuit to the capture register, compares the processed data stored in the captu

Assignees

• Toshiba Kk

Inventors

• Anzou Kenichi

Classifications

• G11C2029/0405

  comprising complete test loop · CPC title

• G11C2029/1208

  Error catch memory · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/4401 Primary

  for self repair · CPC title

• G11C2029/0407

  on power on · CPC title