Storage element, storage device, and signal processing circuit

Patent metadata

Field	Value
Publication number	US-9330759-B2
Application number	US-201514702817-A
Country	US
Kind code	B2
Filing date	May 4, 2015
Priority date	Jan 5, 2011
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

First claim

What is claimed is:

1. A signal processing circuit comprising:
a register, the register comprising:
a first storage circuit; and
a second storage circuit, the second storage circuit comprising:
a capacitor comprising a pair of electrodes;
a first transistor; and
a second transistor,

wherein the first storage circuit is a volatile storage circuit,
wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,
wherein the second transistor comprises a channel formation region comprising a silicon,
wherein one of a source and a drain of the first transistor is electrically connected to one of the pair of electrodes and a gate of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the first storage circuit, and
wherein one of a source and a drain of the second transistor is electrically connected to the first storage circuit.

2. A signal processing circuit comprising:
a register, the register comprising:
a first storage circuit; and
a second storage circuit, the second storage circuit comprising:
a capacitor comprising a pair of electrodes;
a first transistor;
a second transistor; and
a switch comprising a first terminal and a second terminal,

wherein the first storage circuit is a volatile storage circuit,
wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,
wherein the second transistor comprises a channel formation region comprising a silicon,
wherein one of a source and a drain of the first transistor is electrically connected to one of the pair of electrodes and a gate of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the first storage circuit,
wherein one of a source and a drain of the second transistor is electrically connected to the first terminal of the switch, and
wherein the second terminal of the switch is electrically connected to the first storage circuit.

3. A signal processing circuit comprising:
a register, the register comprising:
a first storage circuit; and
a second storage circuit, the second storage circuit comprising:
a capacitor comprising a pair of electrodes;
a first transistor;
a second transistor; and
a third transistor,

wherein the first storage circuit is a volatile storage circuit,
wherein the first transistor comprises a channel formation region comprising an oxide semiconductor material,
wherein one of a source and a drain of the first transistor is electrically connected to one of the pair of electrodes and a gate of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the first storage circuit,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, and
wherein the other of the source and the drain of the third transistor is electrically connected to the first storage circuit.

4. The signal processing circuit according to claim 1 , wherein the oxide semiconductor material is an In—Ga—Zn-based oxide.

5. The signal processing circuit according to claim 1 , wherein the oxide semiconductor material is an In—Sn—Zn-based oxide.

6. The signal processing circuit according to claim 1 , wherein the first storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

7. The signal processing circuit according to claim 1 , wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the first storage circuit.

8. The signal processing circuit according to claim 1 , wherein the one of the source and the drain of the second transistor is electrically connected to an input terminal of the first storage circuit.

9. The signal processing circuit according to claim 2 , wherein the oxide semiconductor material is an In—Ga—Zn-based oxide.

10. The signal processing circuit according to claim 2 , wherein the oxide semiconductor material is an In—Sn—Zn-based oxide.

11. The signal processing circuit according to claim 2 , wherein the first storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

12. The signal processing circuit according to claim 2 , wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the first storage circuit.

13. The signal processing circuit according to claim 2 , wherein the second terminal of the switch is electrically connected to an input terminal of the first storage circuit.

14. The signal processing circuit according to claim 3 , wherein the oxide semiconductor material is an In—Ga—Zn-based oxide.

15. The signal processing circuit according to claim 3 , wherein the oxide semiconductor material is an In—Sn—Zn-based oxide.

16. The signal processing circuit according to claim 3 , wherein the first storage circuit is configured to hold data only in a period during which a power supply voltage supplied.

17. The signal processing circuit according to claim 3 , wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the first storage circuit.

18. The signal processing circuit according to claim 3 , wherein the other of the source and the drain of the third transistor is electrically connected to an input terminal of the first storage circuit.

19. The signal processing circuit according to claim 1 , wherein the first storage circuit is electrically connected to the gate of the second transistor and the one of the pair of electrodes through the first transistor.

Assignees

• Semiconductor Energy Lab

Inventors

• Ohmaru Takuro
• Endo Masami

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G11C11/24 Primary

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• G11C14/0009 Primary

  in which the volatile element is a DRAM cell · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title