Non-volatile latch using spin-transfer torque memory device

Patent metadata

Field	Value
Publication number	US-9330747-B2
Application number	US-201313894266-A
Country	US
Kind code	B2
Filing date	May 14, 2013
Priority date	May 14, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and a buffer to drive complementary signals to the first and second MTJ devices respectively.

First claim

We claim:

1. An apparatus comprising:
a sensing circuit to sense differential resistance;
a first magnetic-tunneling-junction (MTJ) device having a first terminal and a second terminal;
a second MTJ device having a first terminal and a second terminal,
the first and second MTJ devices operable to provide differential resistance,
the sensing circuit coupled to the first terminals of the first and second MTJ devices;

a buffer coupled to the first terminals of the first and second MTJ devices to generate an inverted version of an input data on the first terminal of the first MTJ device and a buffered version of the input data on the first terminal of the second MTJ device; and
a pulse generator to generate self-timed signal to initialize the sensing circuit.

2. The apparatus of claim 1 , wherein the second terminals of the first and second MTJ devices are coupled to a device controllable by a signal.

3. The apparatus of claim 1 , wherein the signal is a clock signal.

4. The apparatus of claim 3 , wherein the buffer comprises drivers gated by the clock signal.

5. The apparatus of claim 1 , wherein the first and second MTJ devices are coupled together in series.

6. The apparatus of claim 1 , wherein the sensing circuit comprises:
cross-coupled transistors; and
an enable transistor coupled to the pulse generator to initialize nodes of the cross-coupled transistors.

7. The apparatus of claim 6 , wherein the pulse generator to turn on the enable transistor during read operation.

8. The apparatus of claim 1 , wherein a fixed magnetic layer of the first MTJ device is coupled to the fixed magnetic layer of the second MTJ device.

9. The apparatus of claim 1 , wherein free magnetic layers of the first and second MTJ devices are coupled to the sensing circuit.

10. The apparatus of claim 1 , wherein the first and second MTJ devices are operable to have complementary resistances.

11. The apparatus of claim 1 , wherein the sensing circuit is coupled to a second device controllable by an inverse of the signal.

12. An apparatus comprising:
an array of dual magnetic-tunneling-junction (MTJ) device, wherein each dual MTJ device comprises of a first MTJ device and a second MTJ device;
a plurality of selection units, each of which is coupled to each MTJ device in the array of dual MTJ devices; and
a buffer to generate complementary signals and drive the complimentary signals to the plurality of selection units at the same time.

13. The apparatus of claim 12 further comprises a sensing circuit to sense differential resistance in a selected dual MTJ device from the array.

14. The apparatus of claim 12 , wherein the first MTJ device is coupled in series to the second MTJ device.

15. The apparatus of claim 14 , wherein each of the first and second MTJ devices includes corresponding fixed magnetic layers which are coupled to each other.

16. The apparatus of claim 12 , wherein each of the first and second MTJ devices is coupled to a sensing circuit to sense differential resistance and to generate an output according to the difference resistance.

17. The apparatus of claim 12 , wherein the selection units comprise multiplexers.

18. A system comprising:
a processor including a latch which comprises:
a sensing circuit to sense differential resistance;
a first magnetic-tunneling-junction (MTJ) device having a first terminal and a second terminal;
a second MTJ device having a first terminal and a second terminal,
the first and second MTJ devices operable to provide differential resistance,
the sensing circuit coupled to the first terminals of the first and second MTJ devices;

a pulse generator to generate self-timed signal to initialize the sensing circuit; and
a buffer including drivers gated by the signal coupled to the first terminals of the first and second MTJ devices to drive complementary signals to the first terminals of the first and second MTJ devices respectively;

an antenna; and
a wireless interface coupled to the processor and to the antenna to communicatively link the processor to a wireless network.

19. The system of claim 18 further comprises a display unit.

20. The system of claim 18 , wherein a fixed magnetic layer of the first MTJ device is coupled to the fixed magnetic layer of the second MTJ device.

21. The apparatus of claim 18 , wherein the buffer generating an inverted version of an input data on the first terminal of the first MTJ device and a buffered version of the input data on the first terminal of the second MTJ device.

Assignees

• Wang Yih
• Hamzaoglu Fatih
• Intel Corp

Inventors

• Wang Yih
• Hamzaoglu Fatih

Classifications

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C14/0081

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title