Processor memory optimization via page access counting

Patent metadata

Field	Value
Publication number	US-9330736-B2
Application number	US-201313764928-A
Country	US
Kind code	B2
Filing date	Feb 12, 2013
Priority date	Nov 9, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

To utilize the most efficient memory available to a mobile processor, page access counters may be used to record utilization associated with multiple different memory types. In one embodiment, an operating system routine may analyze the page access counters to determine low utilization pages and high utilization pages to dynamically assign between the multiple different memory types, which may include a more efficient memory type having greater capacity, greater throughput, lower latency, or lower power consumption than a less efficient memory type. As such, in response to detecting a high utilization page in the less efficient memory or a low utilization page in the more efficient memory, contents associated therewith may be copied to the more efficient memory and the less efficient memory, respectively, and virtual-to-physical address mappings may be changed to reflect the reassignment.

First claim

What is claimed is:

1. A method for efficiently utilizing processor memory, comprising:
monitoring, by a software process executing on a processor, page access counters that measure utilization associated with pages in a main memory located beyond a last-level cache accessible to the processor, wherein the main memory comprises at least a first memory having a first physical memory device type based on a first hardware technology and a second memory having a second physical memory device type based on a second hardware technology, and wherein the first memory has greater efficiency than the second memory; and
dynamically changing, by the software process executing on the processor, an assignment associated with at least one of the pages in the main memory between a first physical address space associated with the first memory and a second physical address space associated with the second memory based on the monitored page access counters, wherein dynamically changing the assignment associated with the at least one page comprises:
instructing a first memory controller and a second memory controller to switch the assignment associated with the at least one page between the first physical address space and the second physical address space, wherein the first memory controller is directly coupled between the first memory and an interconnection fabric located beyond the last-level cache and wherein the second memory controller is directly coupled between the second memory and the interconnection fabric; and
changing a mapping associated with a virtual address that the processor uses to access the at least one page to reflect the switched assignment between the first physical address space and the second physical address space, wherein a memory management unit coupled between the processor and the interconnection fabric maintains the mapping associated with the virtual address in one or more page tables, and wherein the page access counters that measure the utilization associated with the pages in the main memory are integrated into the one or more page tables maintained at the memory management unit; and
wherein the first memory comprises a wide input/output (I/O) memory and the second memory comprises a double data rate (DDR) memory.

2. The method of claim 1 , wherein the at least one page comprises a page in the second memory having a high utilization, and wherein dynamically changing the assignment associated with the at least one page further comprises:
instructing the first memory controller and the second memory controller to copy contents associated with at least one page in the second memory that has the high utilization to an available page in the first memory, wherein the at least one page in the second memory that has the high utilization is identified based on the monitored page access counters; and
mapping the virtual address that the processor uses to access the at least one page to a physical address that corresponds to the available page in the first memory.

3. The method of claim 2 , further comprising:
determining that the page in the second memory has the high utilization based on the page access counter associated therewith exceeding a threshold value, wherein the threshold value is defined to avoid excessive reassignments between the first memory and the second memory.

4. The method of claim 1 , wherein the at least one page comprises a page in the first memory having a low utilization, and wherein dynamically changing the assignment associated with the at least one page further comprises:
instructing the first memory controller and the second memory controller to copy contents associated with at least one page in the first memory that has the low utilization to an available page in the second memory, wherein the at least one page in the first memory that has the low utilization is identified based on the monitored page access counters; and
mapping the virtual address that the processor uses to access the at least one page to a physical address that corresponds to the available page in the second memory.

5. The method of claim 1 , wherein the software process executing on the processor comprises one or more of a kernel routine or an operating system routine.

6. The method of claim 1 , wherein the page access counters comprise hardware-based counters integrated into the one or more page tables, and wherein the one or more page tables store mappings between virtual addresses associated with a virtual memory that comprises an entire address range available to the processor and physical addresses associated with the pages in the first memory and the pages in the second memory.

7. The method of claim 6 , wherein the hardware-based counters comprise one or more registers that store counts relating to the utilization associated with the pages in the first memory and the pages in the second memory.

8. The method of claim 1 , further comprising:
determining that the first memory has greater efficiency than the second memory based on the first memory having one or more of greater capacity, greater throughput, lower latency, or lower power consumption than the second memory.

9. The method of claim 8 , wherein the software process executing on the processor comprises one or more of a kernel routine or an operating system routine that determines that the first memory has greater efficiency than the second memory based on one or more predefined criteria that specify the capacity, throughput, latency, and power consumption associated with the first memory and the second memory.

10. The method of claim 8 , wherein the software process executing on the processor comprises one or more of a kernel routine or an operating system routine that determines that the first memory has greater efficiency than the second memory based on a benchmarking process that measures the capacity, throughput, latency, and power consumption associated with the first memory and the second memory.

11. The method of claim 1 , further comprising:
detecting an event associated with the at least one page; and
updating one of the page access counters that measures the utilization associated with the at least one page based on a type associated with the detected event.

12. The method of claim 11 , wherein updating the page access counter comprises incrementing the page access counter associated with the at least one page in response to determining that the type associated with the detected event comprises accessing the at least one page.

13. The method of claim 11 , wherein updating the page access counter comprises resetting the page access counter associated with the at least one page in response to determining that the type associated with the detected event comprises evicting an entry that corresponds to the at least one page from a data structure that maps the virtual address associated with the at least one page to a corresponding physical address associated with the at least one page.

14. The method of claim 1 , wherein the first hardware technology enables chip-level three-dimensional stacking with through silicon via (TSV) interconnects and memory chips stacked upon a system on a chip (SoC) and the second hardware technology uses one or more phase-locked loops (PLLs) to control timing associated with electrical data and clock signals to realize high transfer rates.

15. The method of claim 1 , further comprising:
instructing the first memory controller and the second memory controller to reassign pages in the second memory that have highest utilizations to the first memory until the first memory fills up;
determining that a page in the

Assignees

• Qualcomm Inc

Inventors

• Michalak Gerald Paul

Classifications

• G06F12/023 Primary

  Free address space management · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/10

  Address translation · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic