Generating guiding patterns for directed self-assembly

Patent metadata

Field	Value
Publication number	US-9330228-B2
Application number	US-201514693304-A
Country	US
Kind code	B2
Filing date	Apr 22, 2015
Priority date	Nov 18, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.

First claim

What is claimed is:

1. One or more processor-readable storage devices storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
A: constructing a guiding pattern for a via-type feature group based on seeding positions, wherein the via-type feature group comprises two or more via-type features in a layout design and the seeding positions are initially derived from targeted locations of the two or more via-type features;
B: determining a potential energy function for the guiding pattern, wherein the potential energy function is at least a two-dimensional function and comprises a first portion representing interactions between via-type features in the via-type feature group and a second portion representing wall effects of the guiding pattern;
C: computing simulated locations of the two or more via-type features based on the potential energy function;
D: changing the seeding positions based on differences between the simulated locations and the targeted locations; and
F: repeating operations A through D until one of one or more termination conditions is met.

2. The one or more processor-readable storage devices recited in claim 1 , wherein initial positions of the seeding positions are centers of the corresponding target locations.

3. The one or more processor-readable storage devices recited in claim 1 , wherein the one or more termination conditions comprise whether the simulated locations match the targeted locations.

4. The one or more processor-readable storage devices recited in claim 1 , wherein the one or more termination conditions comprise number of iterations of operations A through D reaches a predetermined number.

5. The one or more processor-readable storage devices recited in claim 1 , wherein the via-type feature group is DSA (Directed-Self-Assembly)-compliant.

6. The one or more processor-readable storage devices recited in claim 1 , wherein the constructing is further based on area ratio information of a di-block copolymer.

7. The one or more processor-readable storage devices recited in claim 1 , wherein the constructing comprises generating polygons centered at the seeding positions.

8. A method, executed by at least one processor of a computer, comprising:
A: constructing a guiding pattern for a via-type feature group based on seeding positions, wherein the via-type feature group comprises two or more via-type features in a layout design and the seeding positions are initially derived from targeted locations of the two or more via-type features;
B: determining a potential energy function for the guiding pattern, wherein the potential energy function is at least a two-dimensional function and comprises a first portion representing interactions between via-type features in the via-type feature group and a second portion representing wall effects of the guiding pattern;
C: computing simulated locations of the two or more via-type features based on the potential energy function;
D: changing the seeding positions based on differences between the simulated locations and the targeted locations; and
F: repeating operations A through D until one of one or more termination conditions is met.

9. The method recited in claim 8 , wherein initial positions of the seeding positions are centers of the corresponding target locations.

10. The method recited in claim 8 , wherein the one or more termination conditions comprise whether the simulated locations match the targeted locations.

11. The method recited in claim 8 , wherein the one or more termination conditions comprise number of iterations of operations A through D reaches a predetermined number.

12. The method recited in claim 8 , wherein the via-type feature group is DSA (Directed-Self-Assembly) compliant.

13. The method recited in claim 8 , wherein the constructing is further based on area ratio information of a di-block copolymer.

14. The method recited in claim 8 , wherein the constructing comprises generating polygons centered at the seeding positions.

15. A system comprising:
one or more processors, the one or more processors programmed to perform a method, the method comprising:
A: constructing a guiding pattern for a via-type feature group based on seeding positions, wherein the via-type feature group comprises two or more via-type features in a layout design and the seeding positions are initially derived from targeted locations of the two or more via-type features;
B: determining a potential energy function for the guiding pattern, wherein the potential energy function is at least a two-dimensional function and comprises a first portion representing interactions between via-type features in the via-type feature group and a second portion representing wall effects of the guiding pattern;
C: computing simulated locations of the two or more via-type features based on the potential energy function;
D: changing the seeding positions based on differences between the simulated locations and the targeted locations; and
F: repeating operations A through D until one of one or more termination conditions is met.

16. The system recited in claim 15 , wherein initial positions of the seeding positions are centers of the corresponding target locations.

17. The system recited in claim 15 , wherein the one or more termination conditions comprise whether the simulated locations match the targeted locations, wherein the one or more termination conditions comprise number of iterations of operations A through D reaches a predetermined number, or both.

18. The system recited in claim 15 , wherein the via-type feature group is DSA (Directed-Self-Assembly) compliant.

19. The system recited in claim 15 , wherein the constructing is further based on area ratio information of a di-block copolymer.

20. The system recited in claim 15 , wherein the constructing comprises generating polygons centered at the seeding positions.

Assignees

• Mentor Graphics Corp

Inventors

• Robles Juan Andres Torres
• Mitra Joydeep
• Ma Yuansheng
• Andreevna Krasnova Polina
• Granik Yuri

Classifications

• G03F7/0002 Primary

  Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping · CPC title

• G06F2111/06

  Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA] · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title