System, method, and computer program product for inserting a gap in information sent from a drive to a host device

Patent metadata

Field	Value
Publication number	US-9330033-B2
Application number	US-201314104468-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Jul 17, 2009
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A system, method, and computer program product are provided for inserting a gap in information sent from a drive to a host device. In operation, one or more commands are received at a drive from a host device. Additionally, information is queued to send to the host device. Furthermore, a gap is inserted in the information to send to the host device such that the host device is capable of sending additional commands to the drive.

First claim

What is claimed is:

1. A method, comprising:
receiving at a drive one or more commands from a host device that is enabled to communicate with the drive using a storage protocol enabling the drive to prevent the host device from sending additional commands;
queuing at the drive information to send to the host device, the information comprising setup information that comprises a Direct Memory Access (DMA) setup;
determining at the drive whether to insert a gap; and
based on the determining, conditionally inserting at the drive the gap to enable the host device to send the additional commands to the drive, wherein the inserting is at a point in time based at least in part on a current command queue depth of the drive.

2. The method of claim 1 , wherein the gap comprises one or more of a time delay and additional information.

3. The method of claim 1 , wherein the inserting is at a point in time based at least in part on an amount of time since a previous one of the received commands was received.

4. The method of claim 1 , wherein a length of the gap is based at least in part on a current command queue depth of the drive.

5. The method of claim 1 , wherein a length of the gap is according to a fixed value.

6. A drive, comprising:
a buffer enabled to queue information to send to a host device, the information comprising setup information that comprises a Direct Memory Access (DMA) setup; and
a controller enabled to conditionally insert a gap to enable the host device to send additional commands to the drive, the conditionally inserting based on a determination by the controller of whether to insert the gap,
wherein the drive is enabled to receive one or more commands from the host device and to communicate with the host device using a protocol comprising a DMA storage protocol enabling the drive to prevent the host device from sending the additional commands, and
wherein the inserting is at a point in time based at least in part on a current command queue depth of the drive.

7. The drive of claim 6 , wherein the gap comprises one or more of a time delay and additional information.

8. The drive of claim 6 , wherein the insertion is at a point in time based at least in part on an amount of time since a previous one of the received commands was received.

9. The drive of claim 6 , wherein a length of the gap is based at least in part on a current command queue depth of the drive.

10. The drive of claim 6 , wherein a length of the gap is according to a fixed value.

11. A tangible non-transitory computer readable medium having a set of instructions stored therein that when executed by a processing element cause the processing element to perform and/or control operations comprising:
receiving one or more commands at a drive from a host device that is enabled to communicate with the drive using a storage protocol enabling the drive to prevent the host device from sending additional commands;
queuing information to send to the host device, the information comprising setup information that comprises a Direct Memory Access (DMA) setup;
determining whether to insert a gap; and
based on the determining, conditionally inserting the gap to enable the host device to send the additional commands to the drive, wherein the inserting is at a point in time based at least in part on a current command queue depth of the drive.

12. The tangible non-transitory computer readable medium of claim 11 , wherein the gap comprises one or more of a time delay and additional information.

13. The tangible non-transitory computer readable medium of claim 11 , wherein a length of the gap is based at least in part on a current command queue depth of the drive.

14. The tangible non-transitory computer readable medium of claim 11 , wherein a length of the gap is according to a fixed value.

15. A system, comprising:
a drive enabled to receive one or more commands from a host device that is enabled to communicate with the drive using a storage protocol, the drive enabled to prevent the host device from sending additional commands;
a buffer enabled to queue information to send to the host device, the information comprising setup information that comprises a Direct Memory Access (DMA) setup;
a controller enabled to determine whether to insert a gap and to conditionally insert the gap to enable the host device to send the additional commands to the drive, wherein the inserting is at a point in time based at least in part on a current command queue depth of the drive.

16. The system of claim 15 , wherein the gap comprises one or more of a time delay and additional information.

17. The system of claim 15 , wherein the insertion is at a point in time based at least in part on at least one of:
an amount of time since a previous one of the received commands was received, and
a current command queue depth of the drive.

18. The system of claim 15 , wherein a length of the gap is according to at least one of:
a current command queue depth of the drive, and
a fixed value.

Assignees

• Seagate Technology Llc

Inventors

• Stenfort Ross John

Classifications

• G06F3/0671

  In-line storage system · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F13/126 Primary

  and has means for transferring I/O instructions and statuses between control unit and main processor · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title