Suppressing virtual address translation utilizing bits and instruction tagging

Patent metadata

Field	Value
Publication number	US-9330018-B2
Application number	US-201313776842-A
Country	US
Kind code	B2
Filing date	Feb 26, 2013
Priority date	Nov 2, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Some embodiments include a method that can store a first physical address in a first entry in a translation lookaside buffer (TLB). The method can configure a first marker in the first entry in the TLB to indicate that hit suppression is allowed for the first entry. The method can detect a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB, and cause purging of certain entries in the TLB. The method can translate a second virtual address for a second instruction into a second physical address. The method can store the second physical address in a second entry. The method can configure a second marker in the second entry in the TLB to indicate that the hit suppression is not allowed for the second entry in the TLB, and that the purging is not allowed for the second entry in the TLB.

First claim

What is claimed is:

1. A method for managing address translations in a multi-processor computer system, the method comprising:
in response to detecting a hit in a translation lookaside buffer of a processor unit for a virtual address corresponding to an instruction,
determining whether an entry corresponding to the hit will be purged from the translation lookaside buffer based, at least in part, on an indication of a change to a page table,
updating a first register in response to the indication of a change to the page table;
copying content of the first register to a second register in response to the update to the first register
determining whether the instruction entered an instruction pipeline of the processor unit after the processor unit received the indication of the change to the page table
allowing the hit in the translation lookaside buffer in response to determining that the instruction entered the pipeline before the processor unit received the indication of the change to the page table;
suppressing the hit in the translation lookaside buffer, by forming new translation lookaside buffer entries in response to determining that the instruction entered the pipeline after the processor unit received the indication of the change to the page table, wherein the new translation lookaside buffer entries are formed without purging the translation lookaside buffer,
blocking access to the page table for address translation of the virtual address for the instruction into a physical address after suppressing the hit and in response to determining that the entry will be purged based, at least in part, on indication of the change to the page table, and
allowing access to the page table for address translation of the virtual address for the instruction into a physical address after suppressing the hit and in response to determining that the entry will not be purged based, at least in part, on the indication of the change to the page table.

2. The method of claim 1 further comprising marking the entry as to be purged in response to a determination that the entry corresponding to the hit will be purged.

3. The method of claim 1 , further comprising after the updating to the first register, copying the content of the first register to the second register at an interruptible point subsequent to receipt of the indication of the change to the page table.

4. The method of claim 3 further comprising associating a tag with each instruction that enters the instruction pipeline of the processor unit, wherein the tag is based on content of the second register.

5. The method of claim 4 , wherein said determining whether the instruction entered the instruction pipeline of the processor unit after the processor unit received the indication of the change to the page table comprises comparing a tag of the instruction with the first register.

Assignees

• IBM

Inventors

• Deutschle Joerg
• Gaertner Ute
• Heller Lisa C

Classifications

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/682

  Multiprocessor TLB consistency · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title