Resilient register file circuit for dynamic variation tolerance and method of operating the same

US9329918B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9329918-B2
Application numberUS-201113976859-A
CountryUS
Kind codeB2
Filing dateDec 28, 2011
Priority dateDec 28, 2011
Publication dateMay 3, 2016
Grant dateMay 3, 2016

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Abstract

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The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

First claim

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The invention claimed is: 1. A register file circuit, comprising: a local bitline stage including a plurality of bitcells, each of the plurality of bitcells having at least one bitline configured to provide a voltage level; and a global bitline stage communicatively coupled to the local bitline stage, the global bitline stage, including: a sampling error detection circuit coupled to the plurality of bitcells and configured to detect a signal that is representative of the volta…

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What does patent US9329918B2 cover?
The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
Who is the assignee on this patent?
Kulkarni Jaydeep P, Bowman Keith A, Tschanz James W, and 2 more
What technology area does this patent fall under?
Primary CPC classification G06F11/1008. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 03 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).