Context control and parameter passing within microcode based instruction routines

Patent metadata

Field	Value
Publication number	US-9329865-B2
Application number	US-201313915227-A
Country	US
Kind code	B2
Filing date	Jun 11, 2013
Priority date	Jun 11, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A processor includes a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine. The processor further includes a first microcode alias storage comprising a first plurality of microcode alias locations and a second microcode alias storage comprising a second plurality of microcode alias locations. The processor further includes a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is configured to select a first one of a) the first microcode alias storage for storage of a parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the parameter location in one of the second plurality of microcode alias locations.

First claim

What is claimed is:

1. A processor comprising:
a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine;
a first microcode alias storage comprising a first plurality of microcode alias locations;
a second microcode alias storage comprising a second plurality of microcode alias locations;
a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is to:
select a first one of a) the first microcode alias storage for storage of a first parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the first parameter location in one of the second plurality of microcode alias locations; and

a first inheritance logic, coupled to an input of the second microcode alias storage, the first inheritance logic to determine whether to inherit the first parameter location from the first microcode alias location of the first microcode alias storage.

2. The processor of claim 1 , wherein the first logic is further to associate the selected one of the first microcode alias storage or the second microcode alias storage to a current context, the processor further comprising:
a context determination logic to:
determine the current context for the first microcode subroutine; and
determine, based on the current context, whether the first parameter location is stored in one of the first plurality of microcode alias locations of the first microcode alias storage or in one of the second plurality of microcode alias locations of the second microcode alias storage.

3. The processor of claim 1 , further comprising:
a parameter location determination logic to:
receive an indication of a particular microcode alias location from the first microcode subroutine; and
determine, based on the indication, the first parameter location stored in the particular microcode alias location of the determined microcode alias storage.

4. The processor of claim 1 , wherein:
the microcode storage is further to store a second microcode subroutine that is called based on operations of the first microcode subroutine; and
the first logic is further to select a second one of a) the first microcode alias storage for storage of a second parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the second parameter location in one of the second plurality of microcode alias locations.

5. The processor of claim 4 , further comprising:
a context determination logic to:
determine, for the first microcode subroutine, a first context and the first microcode alias storage that stores the first parameter location in one of the first plurality of microcode alias locations; and
determine, for the second microcode subroutine, a second context and the second microcode alias storage that stores the second parameter location in one of the second plurality of microcode alias locations.

6. The processor of claim 5 , wherein the first logic is to select the first context during operation of the first microcode subroutine, to select the second context during operation of the second microcode subroutine, and to return to the first context after completion of the second microcode subroutine.

7. The processor of claim 1 , wherein the first parameter location comprises one of a location where source data is stored or a location where result data is to be stored.

8. The processor of claim 1 , wherein the first microcode alias storage comprises a first microcode alias register and the second microcode alias storage comprises a second microcode alias register.

9. The processor of claim 1 , wherein the first parameter location comprises a location in a register.

10. The processor of claim 5 , further comprising:
a destination storage; and
a save logic to save the first context and the first parameter location from the first microcode alias location to the destination storage, wherein the first context and first parameter may be restored from the destination storage.

11. The processor of claim 1 , further comprising:
a third microcode alias storage comprising a third plurality of microcode alias locations;
wherein the first logic is further to select a first one of a) the first microcode alias storage for storage of a second parameter location in one of the first plurality of microcode alias locations, b) the second microcode alias storage for storage of the second parameter location in one of the second plurality of microcode alias locations, or c) the third microcode alias storage for storage of the second parameter location in one of the third plurality of microcode alias locations.

12. A method comprising:
mapping, by a processor, a first parameter location to a first microcode alias location of a first microcode alias storage for use by a first microcode subroutine; and
mapping, by the processor, a second parameter location to a second microcode alias location of a second microcode alias storage for use by a second microcode subroutine, wherein the second microcode alias location of the second microcode alias storage inherits the first parameter location from the first microcode alias location of the first microcode alias storage, and wherein the second parameter location matches the first parameter location.

13. The method of claim 12 , wherein the second microcode subroutine is called based on operations of the first microcode subroutine, the method further comprising:
selecting a first context for the first microcode subroutine, the first context associated with the first microcode alias storage;
selecting a second context for the second microcode subroutine, the second context associated with the second microcode alias storage; and
returning to the first context after completion of the second microcode subroutine.

14. The method of claim 13 , further comprising:
saving the first context and the first parameter location to a destination storage; and
responsive to a restore microinstruction specifying the destination storage, restoring the first parameter location to the first microcode alias location.

15. A system comprising:
an interconnect; and
a processor coupled with the interconnect, the processor comprising:
a microcode storage to store a first microcode subroutine and a microcode caller of the first microcode subroutine;
a first microcode alias storage comprising a first plurality of microcode alias locations;
a second microcode alias storage comprising a second plurality of microcode alias locations; and
a first logic, coupled to the first microcode alias storage and to the second microcode alias storage, wherein the first logic is to:
select a first one of a) the first microcode alias storage for storage of a first parameter location in one of the first plurality of microcode alias locations or b) the second microcode alias storage for storage of the first parameter location in one of the second plurality of microcode alias locations; and
associate the selected one of the first microcode alias storage or the second microcode alias storage to a current context; and

a context determination logic to:
determine the current context for the first microcode subroutine; and
determine, based on the current context, whether the first parameter location is stored in one of the first plurality of microcode alias locations of the first microcode alias storage or in one of the second plurality of microcode alias locations of the second microcode alias storage.

Assignees

• Combs Jonathan D
• Subramaniam Kameswar
• Wiedemeier Jeffrey G
• Intel Corp

Inventors

• Combs Jonathan D
• Subramaniam Kameswar
• Wiedemeier Jeffrey G

Classifications

• G06F9/30054 Primary

  Unconditional branch instructions · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/323

  for indirect branch instructions · CPC title