Intelligent parametric scratchap memory architecture

Patent metadata

Field	Value
Publication number	US-9329834-B2
Application number	US-201214129178-A
Country	US
Kind code	B2
Filing date	Dec 28, 2012
Priority date	Jan 10, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

First claim

What is claimed is:

1. An electronic apparatus comprising:
a processor to perform an operation; and
a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme between different banks of the plurality of parallel memory banks, and each memory bank to include at least two elements per bank word, each memory bank to include a plurality of addressable words per bank, and each word of a specific one of the plurality of banks to include a plurality of elements, wherein the shifted scheme includes the memory subsystem to store data from adjacent lines of the 2D array by shifting a second line of data relative to a first line of data such that data of the second line of data is provided within different ones of the plurality of memory banks, and wherein based on the shifted second line of data to different ones of the plurality of memory banks no two elements of a 2D block from the 2D array are located in different words of a same memory bank.

2. The electronic apparatus of claim 1 , wherein the memory subsystem to store data from adjacent lines of the 2D array by shifting a storage location of one adjacent line of data.

3. The electronic apparatus of claim 1 , wherein the plurality of parallel memory banks to include less than N memory banks, and a memory controller to provide a read or write of 2D blocks of N elements.

4. The electronic apparatus of claim 1 , wherein the memory subsystem is a one level memory subsystem.

5. The electronic apparatus of claim 1 , wherein the processor is a single-instruction-multiple data processor.

6. The electronic apparatus of claim 1 , wherein the processor to receive N data elements in parallel from the memory subsystem.

7. The electronic apparatus of claim 1 , wherein the memory subsystem is provided on-chip with the processor.

8. The electronic apparatus of claim 1 , wherein the processor to perform motion estimation and compensation based on data within the plurality of parallel memory banks.

9. The electronic apparatus of claim 1 , wherein the processor to perform features relating to a finite impulse response (FIR) digital filter.

10. The electronic apparatus of claim 1 , wherein the processor to perform video and image processing applications based on data within the plurality of parallel memory banks.

11. The electronic apparatus of claim 1 , wherein the memory subsystem to provide unaligned access to one dimensional (1D) rows and two dimensional (2D) blocks of elements.

12. An electronic apparatus comprising:
a processor; and
a memory subsystem that includes a plurality of parallel memory banks to store data representing a two-dimensional (2D) array of data, and the 2D array to be accessed with a selected 2D block and to be stored in the plurality of parallel memory banks, each memory bank to include a plurality of addressable words per bank, each word of a specific one of the plurality of banks to include a plurality of elements, wherein the memory subsystem to store data from adjacent lines of the 2D array by shifting a second line of data relative to a first line of data such that data of the second line of data is provided within different ones of the plurality of memory banks, and wherein based on the shifted second line of data to different ones of the plurality of memory banks no two elements of a 2D block from the 2D array are located in different words of a same memory bank.

13. The electronic apparatus of claim 12 , wherein the memory subsystem to store data from adjacent lines of the 2D array by shifting a storage location of one adjacent line of data.

14. The electronic apparatus of claim 12 , wherein each memory bank to include multiple elements per bank word.

15. The electronic apparatus of claim 12 , wherein the memory subsystem is a one level memory subsystem.

16. The electronic apparatus of claim 12 , wherein the processor is a single-instruction-multiple data processor.

17. The electronic apparatus of claim 12 , wherein the processor to receive N data elements in parallel from the memory subsystem.

18. The electronic apparatus of claim 12 , wherein the memory subsystem is provided on-chip with the processor.

19. The electronic apparatus of claim 12 , wherein the memory subsystem to provide unaligned access to one dimensional (1D) rows and two dimensional (2D) blocks of elements.

20. The electronic apparatus of claim 12 , wherein the plurality of parallel memory banks to include less than N memory banks, and a memory controller to provide a read or write of 2D blocks of N elements.

Assignees

• Intel Corp

Inventors

• Jakovljevic Radomir
• Beric Aleksandar
• Van Dalen Edwin
• Milicev Dragan

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F15/8007

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F12/04 Primary

  Addressing variable-length words or parts of words · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title