Capacitive touch panel

Patent metadata

Field	Value
Publication number	US-9329742-B2
Application number	US-201414301712-A
Country	US
Kind code	B2
Filing date	Jun 11, 2014
Priority date	Feb 10, 2014
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A capacitive touch panel provides a partially high-resolution by mixing multiple resolutions. The capacitive touch panel includes a first electrode layer, a second electrode layer, an insulating layer, and a single one integrated circuit chip. The first electrode layer and the second electrode layer respectively include multiple sensor electrodes disposed with uneven density, so that a part of the touch panel has higher resolution, and other part of the touch panel has lower resolution. The capacitive touch panel provides partially higher resolution by adjusting the distribution of the electrodes without increasing the number of pins of the integrated circuit chip.

First claim

What is claimed is:

1. A capacitive touch panel, comprising:
a first electrode layer comprising a plurality of first sensing electrode series linearly arranged along a first direction and disconnected from each other, wherein each of the first sensing electrode series comprises a plurality of first sensing electrodes, one portion of the adjacent first sensing electrodes are spaced by a first wide pitch, another portion of the adjacent first sensing electrodes are spaced by a first narrow pitch, and the first wide pitch is longer than the first narrow pitch;
a second electrode layer comprising a plurality of second sensing electrode series linearly arranged along a second direction and disconnected from each other, wherein the first direction is orthogonal to the second direction;
an insulating layer for electrically insulating the first electrode layer from the second electrode layer; and
a single integrated circuit chip comprising a plurality of driving pins and a plurality of receiving pins, wherein the driving pins are connected to the first sensing electrode series respectively, and the receiving pins are connected to the second sensing electrode series respectively for detecting a capacitance variation, wherein the first wide pitch and the first narrow pitch are along the second direction, the first wide pitch is longer than a value of dividing a sensing length of the capacitive touch panel in the second direction to a number of the driving pins, the first narrow pitch is shorter than a value of dividing the sensing length of the capacitive touch panel in the second direction to the number of the driving pins.

2. The capacitive touch panel of claim 1 , wherein one portion of the adjacent second sensing electrodes are spaced by a second wide pitch, another portion of the adjacent second sensing electrodes are spaced by a second narrow pitch, and the second wide pitch is longer than the second narrow pitch.

3. The capacitive touch panel of claim 2 , wherein the integrated circuit chip comprises a plurality of driving pins and a plurality of receiving pins, the receiving pins are connected to the second sensing electrode series, the second wide pitch and the second narrow pitch are along the first direction, the second wide pitch is longer than a value of dividing a sensing length of the capacitive touch panel in the first direction to a number of the receiving pins, and the second narrow pitch is shorter than a value of dividing the sensing length of the capacitive touch panel in the first direction to the number of the receiving pins.

4. The capacitive touch panel of claim 2 , wherein the second wide pitch is of a length between about 4.5 millimeters and about 6.5 millimeters, and the second narrow pitch is of a length between about 1.5 millimeters and about 2.5 millimeters.

5. The capacitive touch panel of claim 1 , wherein the first wide pitch is of a length between about 4.5 millimeters and about 6.5 millimeters, and the first narrow pitch is of a length between about 1.5 millimeters and about 2.5 millimeters.

6. A capacitive touch panel, comprising:
a first electrode layer comprising a plurality of first sensing electrode series linearly arranged along a first direction and disconnected from each other, wherein each of the first sensing electrode series comprises a plurality of first sensing electrodes, one portion of the adjacent first sensing electrodes are spaced by a first wide pitch, another portion of the adjacent first sensing electrodes are spaced by a first narrow pitch, and the first wide pitch is longer than the first narrow pitch;
a second electrode layer comprising a plurality of second sensing electrode series linearly arranged along a second direction and disconnected from each other, wherein the first direction is orthogonal to the second direction;
an insulating layer for electrically insulating the first electrode layer from the second electrode layer; and
a single integrated circuit chip comprising a plurality of driving pins and a plurality of receiving pins, wherein the driving pins are connected to the first sensing electrode series respectively, and the receiving pins are connected to the second sensing electrode series respectively for detecting a capacitance variation, wherein the first wide pitch and the first narrow pitch are along the first direction, and the first wide pitch is longer than a value of dividing a sensing length of the capacitive touch panel in the first direction to a number of the receiving pins, the first narrow pitch is shorter than a value of dividing the sensing length of the capacitive touch panel in the first direction to the number of the receiving pins.

7. The capacitive touch panel of claim 6 , wherein one portion of the adjacent second sensing electrodes are spaced by a second wide pitch, another portion of the adjacent second sensing electrodes are spaced by a second narrow pitch, and the second wide pitch is longer than the second narrow pitch.

8. The capacitive touch panel of claim 7 , wherein the integrated circuit chip comprises a plurality of driving pins and a plurality of receiving pins, the driving pins are connected to the first sensing electrode series, the second wide pitch and the second narrow pitch are along the second direction, the second wide pitch is longer than a value of dividing a sensing length of the capacitive touch panel in the second direction to a number of the driving pins, and the second narrow pitch is shorter than a value of dividing the sensing length of the capacitive touch panel in the second direction to the number of the driving pins.

9. The capacitive touch panel of claim 7 , wherein the second wide pitch is of a length between about 4.5 millimeters and about 6.5 millimeters, and the second narrow pitch is of a length between about 1.5 millimeters and about 2.5 millimeters.

10. The capacitive touch panel of claim 6 , wherein the first wide pitch is of a length between about 4.5 millimeters and about 6.5 millimeters, and the first narrow pitch is of a length between about 1.5 millimeters and about 2.5 millimeters.

Assignees

• Quanta Comp Inc

Inventors

• Yi Chien-Yu
• Shen Kuo-Liang
• Chen Ching-Feng

Classifications

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F3/0448

  Details of the electrode shape, e.g. for enhancing the detection of touches, for generating specific electric field shapes, for enhancing display quality · CPC title

• G06F3/0445

  using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer · CPC title

• G06F3/0446

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title