Dual input single output regulator for an inertial sensor

Patent metadata

Field	Value
Publication number	US-9329649-B2
Application number	US-201213683937-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Nov 21, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A dual input single output (DISO) regulator, includes a comparator configured to receive a first and second power supply signal and to provide a first compared signal; a first switch configured to couple the first power supply source to an intermediate node, and a second switch configured to couple the second power supply source to the intermediate node; a control logic circuit, coupled to the first comparator, to the first switch, and to the second switch, and configured to receive the compared signal to control the first and the second switch in a first and second operating condition based on the compared signal. The intermediate node being biased by an intermediate power supply signal correlated to the first or second power supply signal. The DISO regulator includes a low-dropout regulator, configured to provide a regulated power supply signal based on the intermediate power supply signal.

First claim

The invention claimed is:

1. A dual input single output regulator, comprising:
a first power supply node configured to have a first power supply signal;
a second power supply node configured to have a second power supply signal;
a first comparator, having first and second input terminals and an output terminal, the first and second input terminals being configured to be electrically coupled to the first and second power supply nodes, respectively, to receive the first and second power supply signals, respectively, and the output terminal being configured to provide a first compared signal indicative of a result of a comparison between the first and second power supply signals, the first comparator being configured to be controlled by an external control signal, to force the first compared signal to a predefined logic value;
a first switch configured to electrically couple the first power supply node to an intermediate node, the first switch having a first control terminal;
a second switch configured to electrically couple the second power supply node to the intermediate node, the second switch having a second control terminal;
a second comparator, having first and second input terminals and an output terminal, the first and second input terminals being configured to be electrically coupled to the first and second power supply nodes, respectively, to receive the first and second power supply signal, respectively, and the output terminal being configured to provide a second compared signal indicative of a result of a comparison between the first and the second power supply signal, the second comparator being configured to be controlled by the external control signal to force the second compared signal to the predefined logic value; and
a control logic circuit, having a first input terminal coupled to the output terminal of the first comparator, a second input terminal coupled to the output terminal of the second comparator, a first output terminal coupled to the first control terminal of the first switch, and a second output terminal coupled to the second control terminal of the second switch, the control logic circuit being configured to receive the first compared signal and to operate the first and second control terminals of the first and the second switches, respectively, to control the first and second switch in first and second operating conditions, respectively, based on the first or second compared signal, wherein:
the control logic circuit is configured to place, during the first operating condition, the first switch in a closed state and the second switch in an open state and, during the second operating condition, to place the second switch in the closed state and the first switch in the open state,
the first switch is configured, when in the closed state, to bias the intermediate node with a first intermediate power supply signal correlated to the first power supply signal, and
the second switch is configured, when in the closed state, to bias the intermediate node with a second intermediate power supply signal correlated to the second power supply signal; and

a low-dropout regulator having an input terminal coupled to said intermediate node and configured to receive the intermediate power supply signals, and an output terminal configured to provide a regulated power supply signal based on said intermediate power supply signals.

2. The dual input single output regulator according to claim 1 , wherein the first switch is formed by first and second transistors connected in series to one another in a back-to-back configuration, said first control terminal of the first switch being formed by gate terminals of the first and second transistors; and the second switch is formed by third and fourth transistors connected in series to one another in a back-to-back configuration, said second control terminal of the second switch being formed by gate terminals of the third and fourth transistors.

3. The dual input single output regulator according to claim 1 , wherein the first compared signal generated by the first comparator is a logic signal having a first value and a second value, the first value of the first compared signal being indicative of the first power supply signal being higher than, or equal to, the second power supply signal, and the second value of the first compared signal being indicative of the first power supply signal being lower than the second power supply signal.

4. The dual input single output regulator according to claim 3 , wherein the control logic circuit includes an inverter circuit configured to couple the output terminal of the first comparator to the second output terminal of the control logic circuit and configured to generate an inverted signal, the first output terminal of the control logic circuit being coupled to the output terminal of the first comparator in such a way that the signal present at the first output of the control logic circuit has a logic value opposite to a logic value of the inverted signal present at the second output of the control logic circuit.

5. The dual input single output regulator according to claim 3 , further comprising a first level shifter configured to couple the first output terminal of the control logic circuit to the first control terminal of the first switch, configured to receive the first compared signal generated by the first comparator and to bias the control terminal of the first switch with a first shifted signal which is a logic signal having a first value and a second value scaled with respect to the first value and second value, respectively, of the first compared signal.

6. The dual input single output regulator according to claim 4 , further comprising a second level shifter configured to couple the inverter circuit to the second control terminal of the second switch, configured to receive the inverted signal generated by the inverter circuit and to bias the second control terminal of the second switch with a second shifted signal which is a logic signal having a first value and a second value scaled with respect to the first value and second value, respectively, of the inverted signal.

7. The dual input single output regulator according to claim 1 , wherein:
the control logic circuit is configured to:
receive the predefined logic value at the first input terminal, and
receive the second compared signal at the second input terminal.

8. The dual input single output regulator according to claim 1 , wherein the control logic circuit comprises an OR logic device having a first input terminal coupled to the first input terminal of the control logic circuit, a second input terminal coupled to the second input terminal of the control logic circuit, and an output terminal, configured to generate a logic OR signal, and
wherein the predefined value is a “0” logic value so that the logic OR signal corresponds to the received first or second compared signal.

9. The dual input single output regulator according to claim 8 , wherein the control logic circuit includes an inverter circuit configured to couple the output terminal of the OR logic device to the second control terminal of the second switch, the inverter circuit being configured to receive the logic OR signal having a first logic value and generate and inverted signal having a second logic value opposite to the first logic value.

10. The dual input single output regulator according to claim 1 , wherein the first comparator is a high performance, high consumption comparator and the second comparator is a low performance, low consumption comparator.

11. The dual input single output regulator according to claim 1 wherein the first comparator is a low performance, low consu

Assignees

• St Microelectronics Srl

Inventors

• Gasparini Alessandro
• Donadel Andrea
• Ramorini Stefano

Classifications

• Y10T307/696

  Cross-Sectional Technologies · mapped topic

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title