Array substrate and manufacturing method thereof, display device

Patent metadata

Field	Value
Publication number	US-9329448-B2
Application number	US-201314055083-A
Country	US
Kind code	B2
Filing date	Oct 16, 2013
Priority date	Oct 17, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a plurality of pixel units, a plurality of gate lines and positive temperature coefficient (PTC) thermistors. The pixel units are arranged in a matrix and include a plurality of pixel rows and a plurality of pixel columns. Each pixel unit includes a common electrode and a thin-film transistor (TFT). The gate lines are arranged corresponding to each pixel row respectively and connected to the TFT of each pixel unit of a corresponding pixel row respectively. The PTC thermistors are configured to respectively connect the common electrode of each pixel unit to any one of gate lines arranged corresponding to any pixel row except the pixel row in which the pixel unit is disposed.

First claim

What is claimed is:

1. An array substrate, comprising:
a plurality of pixel units arranged in a matrix and including a plurality of pixel rows and a plurality of pixel columns,
each pixel unit including a common electrode and a thin-film transistor (TFT); a plurality of gate lines arranged corresponding to each pixel row respectively and connected to the TFT of each pixel unit in a corresponding pixel row respectively; and
positive temperature coefficient (PTC) thermistors configured to respectively connect the common electrode of each pixel unit to any one of gate lines arranged corresponding to any pixel row except the pixel row in which the pixel unit is disposed.

2. The array substrate according to claim 1 , wherein the common electrode of each pixel unit is connected to a gate line arranged corresponding to a pixel row adjacent to the pixel row in which the pixel unit is disposed.

3. The array substrate according to claim 2 , wherein at least a part of each PTC thermistor is arranged to be overlapped with a corresponding common electrode; and the gate lines connected to the PTC thermistors are arranged on the PTC thermistors.

4. The array substrate according to claim 2 , wherein the PTC thermistors are arranged on the gate lines connected thereto; and at least a part of each common electrode is arranged to be overlapped with a corresponding PTC thermistor.

5. The array substrate according to claim 1 , wherein the PTC thermistors and the gate lines connected thereto have same patterns.

6. The array substrate according to claim 1 , wherein the PTC thermistors are made of organic polymer PTC conductive materials.

7. The array substrate according to claim 1 , wherein each pixel unit further includes a pixel electrode configured to form an electric field together with the common electrode; a gate electrode of the TFT of each pixel unit is connected to a corresponding gate line; and a drain electrode of the TFT is connected to the pixel electrode.

8. The array substrate according to claim 2 , wherein the common electrode of each pixel unit is connected to a gate line in an adjacent row next to the pixel row in which the pixel unit is disposed through the PTC thermistor; the array substrate further comprises a redundant gate line; and the common electrode of each pixel unit in the last pixel row is connected to the redundant gate line.

9. The array substrate according to claim 2 , wherein the common electrode of each pixel unit is connected to a gate line in an adjacent row previous to the pixel row in which the pixel unit is disposed through the PTC thermistor; the array substrate further comprises a redundant gate line; and the common electrode of the pixel unit in the first pixel row is connected to the redundant gate line.

10. The array substrate according to claim 1 , wherein a threshold voltage of the TFT is greater than a difference between a maximum voltage of a data line and a low voltage of the gate electrode.

11. A display device, comprising the array substrate according to claim 1 .

12. A method for manufacturing an array substrate, comprising the following steps of: forming a plurality of common electrodes, a plurality of positive temperature coefficient (PTC) thermistors and a plurality of gate lines in this order or in a reverse order; and forming a gate insulating layer, a semiconductor layer, a data line layer, a surface protective layer and a pixel electrode layer in this order; wherein the plurality of common electrodes are arranged in a matrix and include a plurality of electrode rows and a plurality of electrode columns; the plurality of PTC thermistors are arranged corresponding to the plurality of common electrodes respectively; the plurality of gate lines are arranged corresponding to each electrode row respectively; and each common electrode is connected to a gate line corresponding to an electrode row adjacent to the electrode row in which the common electrode is disposed through a corresponding PTC thermistor.

13. The manufacturing method according to claim 12 , wherein the PTC thermistors and the gate lines have same patterns.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Xi Yusheng
• Liu Jiarong
• Hu Haichen
• Zhang Chunbing

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/1333

  Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence) · CPC title

• G02F2201/40

  Arrangements for improving the aperture ratio · CPC title

• G02F2201/121

  common or background · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title