Deep level transient spectrometer

Patent metadata

Field	Value
Publication number	US-9329223-B2
Application number	US-201213540151-A
Country	US
Kind code	B2
Filing date	Jul 2, 2012
Priority date	Jun 30, 2011
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A method for detecting surface and bulk deep states in semiconductor materials is provided. In various embodiments, the method comprises configuring a detection circuit of charge based deep level transient spectrometer in one of a parallel mode and a series mode by controlling the configuration of a switching circuit of the detection circuit. The method additionally comprises generating digitized voltage charge outputs of a device under test utilizing the detection circuit as controlled via execution of an analog-to-digital conversion and timing program by a control system of the charge based deep level transient spectrometer. Furthermore, the method comprises obtaining desired information about deep level transients of the device under test based on the digitized voltage charge outputs via execution of a control system operable to execute a Q-DLTS data analysis program by the control system.

First claim

What is claimed is:

1. A method for detecting surface and bulk deep states in semiconductor materials, said method comprising:
setting a switch of a switching device of a detection circuit of charge based deep level transient spectrometer to one of a closed position to configure the detection circuit in a parallel mode, wherein the the detection circuit is configured to test a first type of semiconductor material, and an open position to configure the detection circuit in a series mode, wherein the the detection circuit is configured to test a first type of semiconductor material,
inputting, via a user interface of the detection circuit user defined inputs, the user defined inputs comprising:
a charging time during which traps of a device under test will be excited;
a delay time during which integration of charge outputs from the device under test will wait to avoid the integration of switching transients;
a read period for defining a duration of a single cycle for the excitation of the traps and a discharge of the charge output of the device under test;
a number of sample array averages defining a number of iterations that a sample amplitude array parameter is averaged to increase the signal-to-noise ratio;
a sampling rate defining a number of samples per unit time taken from a voltage charge output signal which are used to populate an amplitude and time array; and
a number of samples points defining a size of the amplitude and time array;

inputting to the device under test, via a data acquition module of the detection circuit, excitation voltage pulses based on the input user defined inputs and the switch setting, and via execution of an analog-to-digital conversion and timing program by a control system of the charge based deep level transient spectrometer;
sampling, via the data acquistion module, digitized voltage charge outputs of the device under test generated in response to the input excitation voltage pulses, based on the user inputs and via execution of the analog-to-digital conversion and timing program by the control system; and
obtaining at least one of a trap density, a trap emission rate, and a trap activation energy for deep level transients of the device under test based on the digitized voltage charge outputs via execution of a Q-DLTS data analysis program by the control system.

2. The method of claim 1 , wherein sampling the digitized voltage charge outputs of the device under test utilizing the detection circuit as controlled via execution of an analog-to-digital conversion and timing program further comprises converting the charge outputs of the device under test to the voltage charge outputs and amplifying the voltage charge outputs based on the user inputs utilizing an integration circuit of the detection circuit controlled by the data acquisition module via execution of the analog-to-digital conversion and timing program.

3. The method of claim 2 , wherein sampling the digitized voltage charge outputs of the device under test utilizing the detection circuit as controlled via execution of an analog-to-digital conversion and timing program further comprises further amplifying the amplified voltage charge outputs from the integration circuit based on the user inputs utilizing a secondary amplifier of the detection circuit as controlled by the data acquisition module via execution of the analog-to-digital conversion and timing program.

4. The method of claim 3 wherein sampling the digitized voltage charge outputs of the device under test utilizing the detection circuit as controlled via execution of an analog-to-digital conversion and timing program further comprises further comprises converting the voltage charge outputs to digital signals based on the user inputs via execution of an analog-to-digital conversion and timing program by the control system.

5. The method of claim 4 , further comprising generating the amplitude and time array utilzing the digitized voltage charge output signals based on the user inputs via execution of an analog-to-digital conversion and timing program by the control system.

6. The method of claim 5 wherein obtaining at least one of a trap density, a trap emission rate, and a trap activation energy for the deep level transients of the device under test based on the digitized voltage charge outputs comprises fetching data from the amplitude and time array and computing the at least one of a trap density, a trap emission rate, and a trap activation energy for deep level transients via execution of a control system operable to execute a Q-DLTS data analysis program by the control system.

7. A device for detecting surface and bulk deep states in semiconductor materials, said device comprising:
a control system comprising:
an electronic storage device structured and operable to store an analog-to-digital conversion and timing program and a Q-DLTS data analysis program;
a processor structured and operable to execute the analog-to-digital conversion and the timing program and a Q-DLTS data analysis program; and
a user interface structured and operable to receive user defined inputs, the user defined inputs comprising:
a charging time during which traps of a device under test will be excited;
a delay time during which integration of charge outputs from the device under test will wait to avoid the integration of switching transients;
a read period for defining a duration of a single cycle for the excitation of the traps and a discharge of the charge output of the device under test:
a number of sample array averages defining a number of iterations that a sample amplitude array parameter is averaged to increase the signal-to-noise ratio;
a sampling rate defining a number of samples per unit time taken from a voltage charge output signal which are used to populate an amplitude and time array; and
a number of samples points defining a size of the amplitude and time array; and

a detection circuit structured and operable to input voltage pulses to a device under test based on the input user defined inputs and via execution of an analog-to-digital conversion and timing program by the control system, and sample digitized charge outputs of the device under test resulting from the voltage pulses, based on the user inputs and via execution of the analog-to-digital conversion and timing program by the control system, the detection circuit comprising:
a switching circuit structured and operable to configure the detection circuit in one of a parallel mode and a series mode;
an integration circuit structured and operable to convert the charge outputs of the device under test to the digitized voltage charge outputs and amplify the digitized voltage charge outputs;
a secondary amplifier structured and operable to further amplify the amplified digitized voltage charge outputs from the integration circuit;
a data acquisition module operable to control the provision and timing of the voltage pulses to the device under test, the operation of the switching circuit, and the operation of the integration circuit, wherein

the control system is further structured and operable to execute the Q-DLTS data analysis program to obtain at least one of a trap density, a trap emission rate, and a trap activation energy for the deep level transients of the device under test based on the digitized voltage charge outputs.

8. The device of claim 7 , wherein the detection circuit is configured in the parallel mode when the device under test comprises a semiconductor device.

9. The device of claim 7 , wherein the detection circuit is configured in the serial mode when the device under test comprises a sensor.

Assignees

• Montenegro Daniel E
• Rothenberger Jason B
• Prelas Mark A
• Tompson Jr Robert V
• Tipton Annie
• Univ Missouri

Inventors

• Montenegro Daniel E
• Rothenberger Jason B
• Prelas Mark A
• Tompson Jr Robert V
• Tipton Annie

Classifications

• G01R31/2648 Primary

  Characterising semiconductor materials (testing of materials or semi-finished products G01R31/2831; testing during manufacture H10P74/00) · CPC title