Multilayer ceramic capacitor and board having the same mounted thereon

Patent metadata

Field	Value
Publication number	US-9326381-B2
Application number	US-201414259011-A
Country	US
Kind code	B2
Filing date	Apr 22, 2014
Priority date	Jun 14, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A multilayer ceramic capacitor may include: a ceramic body including dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other; an active layer configured to form capacitance by including first and second internal electrodes facing each other with one dielectric layer therebetween and alternately exposed to the first or second side surface; upper and lower cover layers disposed on and below the active layer; and a first external electrode disposed on the first side surface and a second external electrode disposed on the second side surface. Thickness T and width W of the ceramic body satisfy 0.75W≦T≦1.25W, gap G between the first and second external electrodes satisfies 30 μm≦G≦0.9W, and an average number of dielectric grains in a single dielectric layer in a thickness direction thereof is 2 or greater.

First claim

What is claimed is:

1. A multilayer ceramic capacitor, comprising:
a ceramic body including dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other;
an active layer including a plurality of first and second internal electrodes disposed to face each other with at least one of the dielectric layers interposed therebetween and alternately exposed to the first or second side surface;
upper and lower cover layers disposed on and below the active layer, respectively; and
a first external electrode disposed on the first side surface of the ceramic body and electrically connected to the first internal electrodes and a second external electrode disposed on the second side surface and electrically connected to the second internal electrodes,
wherein when a thickness of the ceramic body is defined as T and a width thereof is defined as W, 0.75W≦T≦1.25W is satisfied,
when a gap between the first and second external electrodes is defined as G, 30 μm≦G≦0.9W is satisfied, and
an average number of dielectric grains in a single dielectric layer in a thickness direction thereof is 2 or greater.

2. The multilayer ceramic capacitor of claim 1 , wherein the lower cover layer has a thickness of 10 μm to 100 μm.

3. The multilayer ceramic capacitor of claim 1 , wherein when the thickness of the ceramic body is a distance between the first and second main surfaces, the width of the ceramic body is a distance between the first side surface on which the first external electrode is formed and the second side surface on which the second external electrode is formed, and a length of the ceramic body is a distance between the first and second end surfaces, the distance between the first and second side surfaces is shorter than or equal to the distance between the first and second end surfaces.

4. The multilayer ceramic capacitor of claim 3 , wherein when the length and the width of the ceramic body are defined as L and W, respectively, 0.5L≦W≦L is satisfied.

5. The multilayer ceramic capacitor of claim 1 , wherein an average grain size of the dielectric grains is 50 nm to 500 nm.

6. The multilayer ceramic capacitor of claim 1 , wherein the first and second internal electrodes are spaced apart from the first and second end surfaces of the ceramic body by a predetermined distance.

7. The multilayer ceramic capacitor of claim 1 , wherein the first and second external electrodes are extended to portions of the first and second main surfaces of the ceramic body.

8. A board having a multilayer ceramic capacitor mounted thereon, the board comprising:
a printed circuit board having two or more electrode pads formed thereon;
the multilayer ceramic capacitor mounted on the printed circuit board; and
a solder connecting the electrode pads and the multilayer ceramic capacitor,
wherein the multilayer ceramic capacitor includes:
ceramic body including dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other;
an active layer including a plurality of first and second internal electrodes disposed to face each other with at least one of the dielectric layers interposed therebetween and alternately exposed to the first or second side surface;
upper and lower cover layers disposed on and below the active layer, respectively; and
a first external electrode disposed on the first side surface of the ceramic body and electrically connected to the first internal electrode and a second external electrode disposed on the second side surface and electrically connected to the second internal electrode,
when a thickness of the ceramic body is defined as T and a width thereof is defined as W, 0.75W≦T≦1.25W is satisfied,
when a gap between the first and second external electrodes is defined as G, 30 μm≦G≦0.9W is satisfied, and
an average number of dielectric grains in a single dielectric layer in a thickness direction thereof is 2 or greater.

9. The board of claim 8 , wherein the lower cover layer has a thickness of 10 μm to 100 μm.

10. The board of claim 8 , wherein when the thickness of the ceramic body is a distance between the first and second main surfaces, the width of the ceramic body is a distance between the first side surface on which the first external electrode is formed and the second side surface on which the second external electrode is formed, and a length of the ceramic body is a distance between the first and second end surfaces, the distance between the first and second side surfaces is shorter than or equal to the distance between the first and second end surfaces.

11. The board of claim 10 , wherein when the length and the width of the ceramic body are defined as L and W, respectively, 0.5L≦W≦L is satisfied.

12. The board of claim 8 , wherein an average grain size of the dielectric grains is 50 nm to 500 nm.

13. The board of claim 8 , wherein the first and second internal electrodes are spaced apart from the first and second end surfaces of the ceramic body by a predetermined distance.

14. The board of claim 8 , wherein the first and second external electrodes are extended to portions of the first and second main surfaces of the ceramic body.

15. The board of claim 8 , wherein the solder is disposed around portions of the first and second external electrodes of the multilayer ceramic capacitor.

16. The board of claim 8 , wherein the solder is disposed around central portions of the first and second external electrodes of the multilayer ceramic capacitor.

17. The board of claim 8 , wherein the electrode pads include first and second electrode pads connected to the first and second external electrodes of the multilayer ceramic capacitor, respectively.

18. The board of claim 17 , wherein the first and second electrode pads are offset to each other in a width direction of the multilayer ceramic capacitor.

19. The board of claim 8 , wherein the electrode pads include:
first and second electrode pads connected to the first external electrode of the multilayer ceramic capacitor; and
third and fourth electrode pads connected to the second external electrode of the multilayer ceramic capacitor.

Assignees

• Samsung Electro Mech

Inventors

• Lee Byoung Hwa
• Park Heung Kil
• Lee Kyo Kwang
• Ahn Young Ghyu
• Park Sang Soo
• Lee Soon Ju

Classifications

• H01G4/12 Primary

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H05K2201/2045

  Protection against vibrations · CPC title

• H05K2201/0979

  Redundant conductors or connections, i.e. more than one current path between two points · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H05K1/111 Primary

  Pads for surface mounting, e.g. lay-out · CPC title