Semiconductor device manufacturing method and semiconductor mounting substrate

Patent metadata

Field	Value
Publication number	US-9326372-B2
Application number	US-201514682024-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Mar 18, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-members.

First claim

What is claimed is:

1. A semiconductor mounting substrate comprising:
a first substrate on which a plurality of traces and a plurality of first electrodes are formed, each of the plurality of first electrodes being connected to one of the plurality of first traces; and
a second substrate in which a plurality of through holes corresponding to the plurality of first electrodes and a plurality of relay members are disposed, each of the plurality of relay members being formed of solder, penetrating through one of the plurality of through holes, projecting from both ends of the one of the plurality of through hole, and having one end connected to one of the plurality of first electrode,
wherein the plurality of relay members have upper surfaces on a single plane opposite to the first substrate across the second substrate.

2. The semiconductor mounting substrate according to claim 1 ,
wherein the second substrate is a planar base material that is formed of a single insulating material and has the plurality of through holes and the plurality of relay members disposed therein.

3. The semiconductor mounting substrate according to claim 2 ,
wherein the first substrate is a built-up substrate having a core layer formed of the insulating material or a batch process laminated substrate including a plurality of laminated insulating plates, each having a wiring pattern disposed thereon and being formed of the insulating material.

4. The semiconductor mounting substrate according to claim 2 ,
wherein the insulating material is polyimide.

Assignees

• Fujitsu Ltd

Inventors

• Kurashina Mamoru
• Mizutani Daisuke

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07234

  Using a reflow oven · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title