Method and system for processing digital data, corresponding apparatus and computer program product

Patent metadata

Field	Value
Publication number	US-9325450-B2
Application number	US-201514667147-A
Country	US
Kind code	B2
Filing date	Mar 24, 2015
Priority date	May 21, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Digital data signals such as, e.g., turbo-encoded data signals subject to decoding, are processed by producing a plurality of families of metrics for these signals while allowing one or more of these metrics to wrap through a respective independent wrapping operation. A decoder, e.g., a decoder for turbo-encoded digital signals computes differences of metrics selected out of the plurality of families of metrics by excluding differences of metrics derived through independent wrapping operations (e.g., wrapping metrics from different families) and generates signals representative of order relationships of combinations of corresponding unwrapped metrics as a function of said differences.

First claim

The invention claimed is:

1. A method, comprising:
automatically producing from digital data signals a plurality of families of metrics, at least one family of the plurality of families allowing metric wrapping;
automatically computing a set of differences of metrics selected out of said plurality of families of metrics, the set of differences excluding differences between wrapping metrics of different families of the plurality of families of metrics;
automatically generating signals representative of order relationships of combinations of corresponding unwrapped metrics based on said set of differences; and
automatically decoding encoded data in the digital data signals based on the generated signals representative of order relationships.

2. The method of claim 1 wherein with α I , α II , . . . , α N being said families of metrics, α I ={α k I I , k I εK I }, α II ={α k II II , k II εK II }, . . . , α N ={α k N N , k N εK N }, K I , K II , . . . , K N a set of indices with |α k n n −α h n n |<D α n /2∀k n , h n εK n , ∀n=I, II, . . . N, and D α n a family wrapping modulo, the method comprises:
allowing at least one metric in said families of metrics α I , α II , . . . , α N to wrap in a respective family wrapping interval, and
checking as a function of differences including wrapped metrics

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 if an order relationship

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 exists between corresponding unwrapped metrics.

3. The method of claim 1 wherein said digital data signals are arranged in data blocks, each data block including a sequence of bit signals and being encoded with a convolutional code, the method comprising, for a data block:
producing for the data block a plurality of families of metrics, at least one family of the plurality of families allowing metric wrapping;
computing for the block a set of differences of metrics selected out of said plurality of families of metrics, the set of differences of metrics for the block excluding differences between wrapping metrics of different families of the plurality of families of metrics for the block;
computing extrinsic information for the block as a function of said set of differences of said metrics for the block; and
decoding the block based on said extrinsic information for the block.

4. The method of claim 3 wherein said data blocks are encoded with a turbo code.

5. The method of claim 3 wherein computing extrinsic information for the block includes selecting dot triplets as a function of said set of differences of said metrics for the block and computing extrinsic information from said dot triplets.

6. The method of claim 3 wherein computing extrinsic information for the block includes combining a set of extrinsic log-likelihood constituents.

7. The method of claim 3 including producing metrics selected out of:
present metrics;
branch metrics;
past metrics;
forward metrics;
future metrics;
backward metrics;
a posteriori metrics; and
extrinsic metrics.

8. A device, comprising:
an input configured to receive digital data signals;
digital signal processing circuitry configured to:
produce from digital data signals a plurality of families of metrics, at least one family of the plurality of families allowing metric wrapping;
compute a set of differences of metrics selected out of said plurality of families of metrics, the set of differences excluding differences between wrapping metrics of different families of the plurality of families of metrics;
generate signals representative of order relationships of combinations of corresponding unwrapped metrics based on said set of differences; and
decode the digital data signals based on the generated signals representative of order relationships.

9. The device of claim 8 wherein, with α I , α II , . . . , α N being said families of metrics, α I ={α k I I , k I εK I }, α II ={α k II II , k II εK II }, . . . , α N ={α k N N , k N εK N }, K I , K II , . . . , K N a set of indices with |α k n n −α h n n |<D α n /2∀k n , h n εK n , ∀n=I, II, . . . N, and D α n a family wrapping modulo, the digital signal processing circuitry is configured to:
allow at least one metric in said families of metrics α I , α II , . . . , α N to wrap in a respective family wrapping interval, and
check as a function of differences including wrapped metrics

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Assignees

• St Microelectronics Srl

Inventors

• Guerrieri Lorenzo
• Bisaglia Paola
• Martina Maurizio
• Masera Guido

Classifications

• H03M13/6586

  Modulo/modular normalization, e.g. 2's complement modulo implementations · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title

• H04L1/0059

  Convolutional codes · CPC title

• H04L1/0058

  Block-coded modulation · CPC title

• H04L1/0054 Primary

  Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title