Adaptive multi-core, multi-direction turbo decoder and related decoding method thereof

Patent metadata

Field	Value
Publication number	US-9325351-B2
Application number	US-201313798109-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A turbo decoder includes a plurality of decoder cores arranged for parallel decoding of a plurality of code segments of a code block in an iteration. Each of the decoder cores is arranged to decode a corresponding code segment according to a sliding window having a window size smaller than a length of the corresponding code segment in most cases, and sequentially generate a plurality of decoded soft outputs each derived from decoding an encoded soft input selected from the corresponding code segment by the sliding window.

First claim

What is claimed is:

1. A turbo decoder comprising:
a plurality of decoder cores, each arranged to decode a different corresponding code segment according to a sliding window, and sequentially generate a plurality of decoded soft outputs each derived from decoding an encoded soft input selected from the corresponding code segment by the sliding window;
wherein in a same iteration, adjacent decoder cores of the plurality of decoder core cores are arranged to obtain different metrics in opposite decoding directions respectively, and in adjacent iterations, one of the plurality of decoder cores is arranged to obtain different metrics in opposite decoding directions.

2. The turbo decoder of claim 1 , wherein the plurality of decoder cores are arranged for parallel decoding of a plurality of code segments of a code block in one iteration.

3. The turbo decoder of claim 1 , wherein in a first iteration, a first decoder core of the plurality of decoder cores is arranged to obtain first metrics of a first code segment in a first decoding direction according to a full trace manner, and obtain second metrics of the first code segment in a second decoding direction according to a partial trace manner, where the second decoding direction is opposite to the first decoding direction.

4. The turbo decoder of claim 3 , wherein in a second iteration following the first iteration, the first decoder core is arranged to obtain the first metrics of the first code segment in the first decoding direction according to the partial trace manner, and obtain the second metrics of the first code segment in the second decoding direction according to the full trace manner.

5. The turbo decoder of claim 3 , wherein the first code segment and a second code segment are successive code segments in a code block; and in the first iteration, a second decoder core of the plurality of decoder cores is arranged to obtain first metrics of the second code segment in the first decoding direction according to a partial trace manner, and obtain second metrics of the second code segment in the second decoding direction according to the full trace manner.

6. The turbo decoder of claim 1 , wherein the turbo decoder has a plurality of pre-defined decoder cores, and further comprises:
a controller, arranged for referring to a throughput requirement to adaptively enable part or all of the pre-defined decoder cores as the plurality of decoder cores for decoding a code block.

7. The turbo decoder of claim 1 , wherein a first encoded soft input, a second encoded soft input and a third encoded soft input are successively selected from the corresponding code segment by the sliding window; and each decoder core comprises:
a first metric computation unit, wherein during a first time period, the first metric computation unit is arranged for computing first metrics of the second encoded soft input in a first decoding direction according to a full trace manner; and
a plurality of second metric computation units, wherein during the first time period, one of the second metric computation units is arranged for computing second metrics of the first encoded soft input in a second decoding direction opposite to the first decoding direction according to a partial trace manner, and another of the second metric computation units is arranged for computing second metrics of the third encoded soft input in the second decoding direction according to the partial trace manner.

8. The turbo decoder of claim 7 , wherein during a second time period preceding the first time period, the first metric computation unit is further arranged for computing first metrics of the first encoded soft input in the first decoding direction according to the full trace manner; and each decoder core further comprises:
a third metric computation unit, wherein during the first time period, the third metric computation unit is arranged for at least computing transition metrics of the first encoded soft input; and
a log-likelihood ratio (LLR) computation unit, wherein during the first time period, the LLR computation unit is arranged for generating a decoded soft output of the first encoded soft input according to the transition metrics, the first metrics and the second metrics of the first code segment.

9. A decoding method comprising:
enabling a plurality of decoder cores in a turbo decoder; and
configuring each of the plurality of decoder cores to decode a different corresponding code segment according to a sliding window, and sequentially generate a plurality of decoded soft outputs each derived from decoding an encoded soft input selected from the corresponding code segment by the sliding window;
wherein in a same iteration, adjacent decoder cores of the plurality of decoder cores are arranged to obtain different metrics in opposite decoding directions respectively, and in adjacent iterations, one of the plurality of decoder cores is arranged to obtain different metrics in opposite decoding directions.

10. The decoding method of claim 9 , wherein the plurality of decoder cores are arranged for parallel decoding of a plurality of code segments of a code block in one iteration.

11. The decoding method of claim 9 , wherein the step of configuring each of the plurality of decoder cores to decode the corresponding code segment comprises:
in a first iteration, configuring a first decoder core of the plurality of decoder cores to obtain first metrics of a first code segment in a first decoding direction according to a full trace manner, and obtain second metrics of the first code segment in a second decoding direction according to a partial trace manner, where the second decoding direction is opposite to the first decoding direction.

12. The decoding method of claim 10 , wherein the step of configuring each of the plurality of decoder cores to decode the corresponding code segment further comprises:
in a second iteration following the first iteration, configuring the first decoder core to obtain first metrics of the first code segment in the first decoding direction according to the partial trace manner, and obtain second metrics of the first code segment in the second decoding direction according to the full trace manner.

13. The decoding method of claim 10 , wherein the first code segment and a second code segment are successive code segments in a code block; and the step of configuring each of the plurality of decoder cores to decode the corresponding code segment further comprises:
in the first iteration, configuring a second decoder core of the plurality of decoder cores to obtain first metrics of the second code segment in the first decoding direction according to a partial trace manner, and obtain second metrics of the second code segment in the second decoding direction according to the full trace manner.

14. The decoding method of claim 10 , wherein the turbo decoder has a plurality of pre-defined decoder cores, and the decoding method further comprises:
referring to a throughput requirement to adaptively enable part or all of the pre-defined decoder cores as the plurality of decoder cores for decoding a code block.

15. The decoding method of claim 10 , wherein a first encoded soft input, a second encoded soft input and a third encoded soft input are successively selected from the corresponding code segment by the sliding window; and the step of configuring each of the plurality of decoder cores to decode the corresponding code segment comprises:
during a first time period, computing first metrics of the second encoded soft input in a first decoding direction according to a full trace manner, computing sec

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Lo Chiaming
• Lee Lawrence Chen

Classifications

• H03M13/3905

  Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding · CPC title

• H03M13/395

  using a collapsed trellis, e.g. M-step algorithm, radix-n architectures with n>2 · CPC title

• H03M13/3972

  using sliding window techniques or parallel windows · CPC title

• H03M13/6525

  3GPP LTE including E-UTRA · CPC title

• H03M13/2957 Primary

  Turbo codes and decoding · CPC title