Apparatus for controlling comparator input offset voltage

Patent metadata

Field	Value
Publication number	US-9325304-B2
Application number	US-201414165595-A
Country	US
Kind code	B2
Filing date	Jan 28, 2014
Priority date	Mar 11, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

An apparatus to remove an input offset voltage of a comparator circuit includes an input voltage offset capacitor, control logic to charge and discharge the capacitor to provide an offset cancelation voltage. The offset cancellation voltage removes the input offset voltage of the comparator dependent upon an output of the comparator circuit. A switching arrangement controlled by the control logic switches signals between the capacitor and the control logic.

First claim

The invention claimed is:

1. An apparatus to remove an input offset voltage of a comparator circuit, comprising:
an input voltage offset capacitor;
control logic operable to charge and discharge the capacitor to provide an offset cancelation voltage to remove the input offset voltage of the comparator circuit dependent upon an output of the comparator circuit; and
a switching arrangement operable under control of the control logic to switch signals between the capacitor and the control logic,
wherein the capacitor removes the input offset voltage of the comparator circuit by altering the body bias voltage of one of a plurality of input transistors of the comparator circuit.

2. The apparatus of claim 1 , wherein the capacitor is arranged between a body of the one of the plurality of input transistors of the comparator circuit and a reference voltage.

3. The apparatus of claim 1 , wherein the control logic comprises a charge control circuit operable to control the charging of the capacitor and a discharge control circuit operable to control the discharging of the capacitor.

4. The apparatus of claim 3 , wherein the control logic comprises at least two NOT gates in series operably coupled to the output of the comparator circuit and arranged to provide a first control signal (OUTA) and a second control signal (OUTB), wherein the first control signal (OUTA) controls the charge control circuit and the second control signal (OUTB) controls the discharge control circuit.

5. The apparatus of claim 4 , wherein the first control signal (OUTA) is the output of the second NOT gate and the second control signal (OUTB) is the output of the first NOT gate.

6. The apparatus of claim 4 , wherein the control logic further comprises a D-latch operably coupled after the two NOT gates to provide a latched output of the comparator circuit under control of a read signal.

7. The apparatus of claim 4 , wherein the charge control circuit is operably dependent upon the first control signal (OUTA) and an offset activation signal, and the discharge control circuit is operably dependent upon the second control signal (OUTB) and the offset activation signal.

8. The apparatus of claim 1 , wherein the switching arrangement comprises a first switch operably coupled between an input signal and a second input of the comparator circuit, and activated by a comparison signal.

9. The apparatus of claim 8 , wherein the switching arrangement comprises a second switch coupled between the second input of the comparator circuit and a first input of the comparator circuit, and activated by an offset activation signal.

10. The apparatus of claim 9 , wherein the switching arrangement comprises a third switch coupled between the second input of the comparator circuit and a reference voltage, and activated by an initialization signal.

11. The apparatus of claim 10 , wherein the first input of the comparator circuit is operably coupled to the reference voltage.

12. The apparatus of claim 10 , wherein the comparator circuit includes the plurality of input transistors and the switching arrangement comprises a fourth switch coupled between a body and a source of one of the input transistors of the comparator circuit having the capacitor coupled thereto.

13. A method of removing an input offset voltage from a comparator comprising:
charging or discharging an input voltage offset capacitor coupled between a body of one of a plurality of input differential transistors forming the comparator when another one of the plurality of input differential transistors forming the comparator has its source and body coupled together;
wherein the charging or discharging of the input voltage offset capacitor occurs in response to a signal dependent upon a change of output of the comparator due to the input offset voltage acting on nominally equal input voltages.

14. The method of claim 13 , further comprising initially charging the input voltage offset capacitor to equal a reference voltage by a plurality of switches.

15. The method of claim 14 , further comprising comparing two inputs voltages with the comparator in a comparison stage after said initial charging.

16. The method of claim 13 , wherein charging is used for an apparent positive input offset voltage acting on an inverting input of the comparator and discharging is used for an apparent negative input offset voltage acting on the inverting input of the comparator.

Assignees

• Wang Meng
• Freescale Semiconductor Inc

Inventors

• Wang Meng

Classifications

• H03K5/2481 Primary

  with at least one differential stage · CPC title