Semiconductor devices and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9324941-B2
Application number	US-201414306976-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Oct 15, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method of fabricating a semiconductor device includes providing a wafer in a chamber of a point-cusp magnetron physical vapor deposition (PCM-PVD) apparatus, the chamber including a metal target. The method further includes providing an inert gas and a reactive gas in the chamber and forming an amorphous conductive layer on the wafer by reacting the reactive gas with a metal atom separated from the metal target by the inert gas.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
providing a wafer in a chamber of a point-cusp magnetron physical vapor deposition (PCM-PVD) apparatus, the chamber including a metal target;
providing an inert gas and a reactive gas in the chamber; and
forming an amorphous metal nitride layer on the wafer by reacting the reactive gas with a metal atom separated from the metal target by the inert gas, the amorphous metal nitride layer including an amorphous titanium nitride layer having an amount of nitrogen that is 3/10 or less than an amount of titanium.

2. The method of claim 1 , wherein
the wafer comprises an interlayer dielectric layer formed thereon, the interlayer dielectric layer including a recess region, and
the forming forms the amorphous metal nitride layer filling the recess region.

3. The method of claim 2 , wherein the recess region comprises a contact hole, the method further comprising:
forming a crystalline conductive pattern filling a lower part of the contact hole before the forming an amorphous metal nitride layer.

4. The method of claim 3 , wherein the forming forms the crystalline conductive pattern by a chemical vapor deposition process.

5. The method of claim 1 , wherein the providing an inert gas and a reactive gas provides the reactive gas including at least one of nitrogen, ammonia, oxygen, and vapor.

6. The method of claim 1 , further comprising:
unloading the wafer from the chamber; and
forming one of a magnetic tunnel junction pattern and a metal line pattern on the amorphous titanium nitride layer.

7. A method for fabricating a magnetic memory device, the method comprising:
patterning an interlayer dielectric layer on a substrate to form a recess region therein;
forming a contact plug filling the recess region, the contact plug including an amorphous titanium nitride layer; and
forming a magnetic tunnel junction pattern on the contact plug ,
wherein the forming a magnetic tunnel junction pattern forms a first magnetic layer, a tunnel barrier layer, and a reference layer on the amorphous titanium nitride layer, and
wherein the reference layer includes a second magnetic layer, a capping layer, a first pinned layer, an exchange-coupling layer, and a second pinned layer that are sequentially stacked on the tunnel barrier layer.

8. The method of claim 7 , wherein the forming a contact plug forms the amorphous titanium nitride layer to include an amount of nitrogen that is 3/10 or less than an amount of titanium.

9. The method of claim 7 , wherein the forming a contact plug forms the amorphous titanium nitride layer constituting a lower electrode.

10. The method of claim 9 , wherein the forming a contact plug forms the amorphous titanium nitride layer including a sidewall aligned with a sidewall of the magnetic tunnel junction pattern.

11. The method of claim 7 , wherein the forming a contact plug forms a crystalline conductive pattern under the amorphous titanium nitride layer.

12. A method for fabricating a magnetic memory device, the method comprising:
forming at least one interlayer dielectric layer on a substrate;
forming a lower contact plug penetrating at least a first portion of the at least one interlayer dielectric layer by a chemical vapor deposition process (CVD);
forming an upper contact plug penetrating at least a second portion of the at least one interlayer dielectric layer by a point-cusp magnetron physical vapor deposition (PCM-PVD) process;
forming a lower electrode on the at least one interlayer dielectric layer; and
forming a magnetic tunnel junction pattern on the lower electrode.

13. The method of claim 12 , wherein
the forming a lower contact plug forms the lower contact plug having a crystalline structure, and
the forming an upper contact plug forms the upper contact plug having an amorphous structure.

14. The method of claim 12 , further comprising:
patterning the at least one interlayer dielectric layer to form a contact hole in the at least one interlayer dielectric layer prior to the forming a lower contact plug, wherein the lower contact plug fills the contact hole.

15. The method of claim 14 , further comprising:
performing an etch-back process to recess an upper portion of the lower contact plug prior to the forming an upper contact plug, wherein the upper contact plug is formed in the recessed upper portion.

16. The method of claim 12 , wherein
the forming at least one interlayer dielectric layer forms first and second interlayer dielectric layers on the substrate,
the forming a lower contact plug forms the lower contact plug to penetrate the first interlayer dielectric layer, and
the forming an upper contact plug forms the upper contact plug to penetrate the second interlayer dielectric layer.

17. The method of claim 12 , wherein the forming a lower electrode forms the lower electrode including an amorphous titanium nitride layer having an amount of nitrogen that is 3/10 or less than an amount of titanium.

18. The method of claim 12 , wherein
the forming a magnetic tunnel junction pattern forms a first magnetic layer, a tunnel barrier layer, and a reference layer on the lower electrode,
the reference layer including a second magnetic layer, a capping layer, a first pinned layer, an exchange-coupling layer, and a second pinned layer that are sequentially stacked on the tunnel barrier layer.

Assignees

• Kim Whankyun
• Kim Woojin
• Lim Woo Chang
• Samsung Electronics Co Ltd

Inventors

• Kim Whankyun
• Kim Woojin
• Lim Woo Chang

Classifications

• H10P32/171

  being group IV material · CPC title

• H10P32/12 Primary

  between a solid phase and a gaseous phase · CPC title

• H01J37/3408

  Planar magnetron sputtering · CPC title

• C23C14/046 Primary

  Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates · CPC title

• H01L43/12 Primary

  Electricity · mapped topic