Fabricating method of thin film transistor, thin film transistor and display panel

Patent metadata

Field	Value
Publication number	US-9324873-B2
Application number	US-201414421931-A
Country	US
Kind code	B2
Filing date	Apr 25, 2014
Priority date	Dec 30, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Embodiments of the invention provide a fabricating method a thin film transistor, a thin film transistor and a display panel, so as to improve carrier mobility in the polycrystalline silicon. The fabricating method a thin film transistor comprises following M 1 , depositing an inducing layer on a substrate; M 2 , etching a recess in the inducing layer by an etching process, the recess having an edge with a prescribed shape; M 3 , depositing an amorphous silicon layer in the recess having an edge with a prescribed shape, and inducing the amorphous silicon layer to form a polycrystalline silicon layer by crystallization method, polycrystalline silicon grains in the polycrystalline silicon layer arranging in a direction vertical to the edge of the recess by the limitation of the edge of the recess, and the polycrystalline silicone layer and the inducing layer together forming a semiconductor layer; and M 4 , forming a gate insulating layer, a gate, a passivation layer and a source and a drain connecting with the semiconductor layer sequentially on the semiconductor layer.

First claim

What is claimed is:

1. A fabricating method of a thin film transistor, comprising following steps:
M 1 , depositing an inducing layer on a substrate;
M 2 , etching a recess in the inducing layer by an etching process, the recess having an edge with a prescribed shape;
M 3 , depositing an amorphous silicon layer in the recess having an edge with a prescribed shape, and inducing the amorphous silicon layer to form a polycrystalline silicon layer by crystallization method, polycrystalline silicon grains in the polycrystalline silicon layer arranging in a direction vertical to the edge of the recess by the limitation of the edge of the recess, and the polycrystalline silicon layer and the inducing layer together forming a semiconductor layer; and
M 4 , forming a gate insulating layer, a gate, a passivation layer and a source and a drain connecting with the semiconductor layer sequentially on the semiconductor layer.

2. The fabricating method according to claim 1 , wherein the step M 2 comprises:
etching a recess in the inducing layer by an etching process, and a plurality of convex portions are formed inwards in a direction vertical to the edge of the recess.

3. The fabricating method according to claim 2 , wherein the plurality of convex portions are serrated.

4. The fabricating method according to claim 2 , wherein the step M 1 comprises:
depositing dense inducing sub-layer and sparse inducing sub-layer alternatively so as to form the inducing layer composed of the dense inducing sub-layer and the sparse inducing sub-layer on the substrate; and
the step M 2 comprises:
etching the inducing layer so that the dense inducing sub-layer and the sparse inducing sub-layer deposited alternatively form a plurality of serrated convex portions correspondingly.

5. The fabricating method according to claim 1 , wherein the inducing layer is made of a material of silicon nitride.

6. The fabricating method according to claim 1 , wherein the polycrystalline silicon layer has an upper surface flush with an upper surface of the inducing layer.

7. The fabricating method according to claim 6 , herein the semiconductor layer has a thickness of 100 nm-200 nm.

8. The fabricating method according to claim 1 , wherein the step of forming a gate insulating layer, a gate, a passivation layer and a source and a drain connecting with the semiconductor layer sequentially on the semiconductor layer comprises:
forming a gate insulating layer and a gate metal layer on the semiconductor layer sequentially, forming pattern of the gate in the gate metal layer by a patterning process;
forming a passivation layer on the gate insulating layer and the gate, and forming through holes for the source and the drain on the gate insulating layer and the passivation layer by a patterning process;
forming a source/drain metal layer on the passivation layer, and photoetching the source/drain metal layer by a patterning process so as to form the source and the drain, the source and drain connect with the semiconductor layer via through holes passing through the gate insulating layer and the passivation layer.

9. A thin film transistor fabricated by a method comprising following steps:
M 1 , depositing an inducing layer on a substrate;
M 2 , etching a recess in the inducing layer by an etching process, the recess having an edge with a prescribed shape;
M 3 , depositing an amorphous silicon layer in the recess having an edge with a prescribed shape, and inducing the amorphous silicon layer to form a polycrystalline silicon layer by crystallization method, polycrystalline silicon grains in the polycrystalline silicon layer arranging in a direction vertical to the edge of the recess by the limitation of the of the recess, and the polycrystalline silicon layer and the inducing layer together forming a semiconductor layer; and
M 4 , forming a gate insulating layer, a gate, a passivation layer and a source and a drain connecting with the semiconductor layer sequentially on the semiconductor layer.

10. The thin film transistor according to claim 9 , wherein a plurality of convex portions are formed inwards in a direction vertical to the edge of the recess.

11. The thin film transistor according to claim 9 , wherein the inducing layer is made of a material of silicon nitride.

12. The thin film transistor according to claim 9 , wherein the polycrystalline silicon layer has an upper surface flush with an upper surface of the inducing layer.

13. The thin film transistor according to claim 12 , wherein the semiconductor layer has a thickness of 100 nm-200 nm.

14. A display panel comprising a thin film transistor fabricated by a method comprising following steps:
M 1 , depositing an inducing layer on a substrate;
M 2 , etching a recess in the inducing layer by an etching process, the recess having an edge with a prescribed shape;
M 3 , depositing an amorphous silicon layer in the recess having an edge with a prescribed shape, and inducing the amorphous silicon layer to form a polycrystalline silicon layer by crystallization method, polycrystalline silicon grains in the polycrystalline silicon layer arranging in a direction vertical to the edge of the recess by the limitation of the edge of the recess, and the polycrystalline silicon layer and the inducing layer together forming a semiconductor layer; and

M 4 , forming a gate insulating layer, a gate, passivation layer and a source and a drain connecting with the semiconductor layer sequentially on the semiconductor layer.

15. The thin film transistor according to claim 14 , wherein the plurality of convex portions are serrated.

16. The display panel according to claim 14 , wherein a plurality of convex portions are formed inwards in a direction vertical to the edge of the recess.

17. The display panel according to claim 16 , wherein the plurality of convex portions are serrated.

18. The display panel according to claim 14 , wherein the inducing layer is made of a material of silicon nitride.

19. The display panel according to claim 14 , wherein the polycrystalline silicon layer has an upper surface flush with an upper surface of the inducing layer.

20. The display panel according to claim 19 , wherein the semiconductor layer has a thickness of 100 nm-200 nm.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics

Inventors

• Li Jing
• Xie Zhenyu
• Chen Xu
• Zhang Wenyu
• Xu Da

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/3806

  using crystallisation-enhancing elements · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title