Epitaxial growth of silicon for FinFETS with non-rectangular cross-sections

Patent metadata

Field	Value
Publication number	US-9324868-B2
Application number	US-201414463057-A
Country	US
Kind code	B2
Filing date	Aug 19, 2014
Priority date	Aug 19, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET.

First claim

What is claimed is:

1. A method comprising:
forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate;
epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region;
forming a gate oxide over and perpendicular to each fin;
forming a gate electrode over the gate oxide to form a FinFET; and
performing a well implantation between each pair of adjacent STI regions either prior to epitaxially growing the silicon-based layer, subsequent to epitaxially growing the silicon-based layer but prior to forming the gate oxide, or prior to anisotropically wet etching the silicon substrate,
wherein the epitaxially grown silicon-based layer forms a fin with a diamond-shaped cross-section between each pair of adjacent STI regions, the diamond-shaped cross section comprising two sides meeting at a single point above the surface of the silicon substrate.

2. The method of claim 1 , wherein the silicon substrate comprises a silicon-on-insulator (SOI) or bulk silicon substrate.

3. The method of claim 1 , wherein the dielectric material is silicon dioxide (SiO 2 ).

4. The method of claim 1 , wherein the epitaxially grown silicon-based layer is p-type or n-type doped silicon.

5. The method of claim 1 , further comprising anisotropically wet etching the silicon substrate from each STI region to each adjacent STI region to form a channel between each pair of adjacent STI regions and epitaxially growing the silicon-based layer in each channel.

6. The method of claim 5 , further comprising planarizing the silicon substrate by chemical-mechanical planarization (CMP) prior to anisotropically wet etching the silicon substrate.

7. The method of claim 5 , comprising anisotropically wet etching the silicon substrate with potassium hydroxide (KOH), ethylene diamine and pyrocatechol (EDP), or tetramethylammonium hydroxide (TMAH).

8. A FinFET comprising:
a silicon substrate;
at least two adjacent but separate shallow trench isolation (STI) regions in the silicon substrate;
a channel formed in the silicon substrate extending from each STI region to each adjacent STI region, the channel having a trapezoidal cross-section;
a fin with a non-rectangular cross-section filling and extending above each channel, wherein each fin is an epitaxially grown silicon-based layer;
a gate oxide over and perpendicular to each fin; and
a gate electrode over the gate oxide,

wherein the non-rectangular cross-section of each fin comprises a diamond-shaped cross-section in each channel, the diamond-shaped cross section comprising two sides meeting at a single point above the surface of the silicon substrate.

9. The FinFET of claim 8 , wherein the silicon substrate comprises a silicon-on-insulator (SOI) or bulk silicon substrate.

10. The FinFET of claim 8 , further comprising at least one additional gate electrode over and perpendicular to each fin, wherein the FinFET is a multi-gate FinFET.

11. A FinFET comprising:
a silicon substrate;
at least two adjacent but separate shallow trench isolation (STI) regions in the silicon substrate;
a fin with a non-rectangular cross-section extending above the silicon substrate extending from each STI region to each adjacent STI region, wherein each fin is an epitaxially grown silicon-based layer;
a gate oxide over and perpendicular to each fin; and
a gate electrode over the gate oxide,
wherein the non-rectangular cross-section of the fin comprises a diamond-shaped cross-section between the at least two adjacent STI regions, the diamond-shaped cross section comprising two sides meeting at a single point above the surface of the silicon substrate.

12. The FinFET of claim 11 , wherein the silicon substrate comprises a silicon-on-insulator (SOI) or bulk silicon substrate.

13. The FinFET of claim 11 , further comprising at least one additional gate electrode over and perpendicular to each fin, wherein the FinFET is a multi-gate FinFET.

Assignees

• Globalfoundries Inc

Inventors

• Yan Ran Ruby
• Richter Ralf
• Hoentschel Jan
• Thees Hans-Jurgen

Classifications

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P14/3451

  Structure · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title