Gate dielectric protection for transistors

Patent metadata

Field	Value
Publication number	US-9324822-B2
Application number	US-201414321679-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Jul 1, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

First claim

What is claimed:

1. A method for forming a transistor, comprising:
forming a source region on a substrate, comprising forming a first n+dopant region on a p-type substrate and forming a first contact region above said first n+dopant region;
forming a drain region on said substrate adjacent said active gate region, comprising forming a second n+dopant region on said p-type substrate and forming a second contact region above said second n+dopant region;
forming an active gate region on said substrate adjacent said source region, comprising forming a first gate oxide region above said p-type substrate between said first and second n+dopant regions and forming a first polysilicon conductor region above said first gate oxide region; and
forming a first inactive gate region on said substrate in parallel to said active gate region, comprising forming a second gate oxide region above said p-type substrate adjacent said first n+dopant region, forming a second polysilicon conductor region above second first gate oxide region, and electrically coupling said second polysilicon conductor region to said first polysilicon conductor region, wherein said source region, said drain region, said active gate region, and said first inactive gate region comprise said transistor, and wherein said first inactive gate region is capable of dissipating at least a portion of a charge.

2. The method of claim 1 , further comprising:
forming a third n+dopant region on said p-type substrate adjacent said second gate oxide region;
forming a shallow trench isolation region adjacent said third n+dopant;
forming a p+dopant region on said p-type substrate adjacent said shallow trench isolation region; and
forming a third contact region above said p+dopant region.

3. The method of claim 2 , further comprising
coupling electrically a source pad to said source region;
coupling electrically a gate pad to said gate region; and
coupling electrically a drain pad to said drain region;
wherein said source, gate and drain pads are capable providing for testing of said transistor.

4. The method of claim 1 , wherein said first inactive gate region is further capable of at least partially dissipating said charge resulting from a plasma process.

5. The method of claim 1 , further comprising forming a second inactive gate region on said substrate in parallel to said first inactive gate, wherein said second inactive gate is capable of dissipating said at least a portion of said charge.

6. A method for forming a transistor, comprising:
forming a source region on a substrate, comprising forming a first p+dopant region on an n-type substrate and forming a first contact region above said first p+dopant region;
forming a drain region on said substrate adjacent said active gate region, comprising forming a second p+dopant region on said n-type substrate and forming a second contact region above said second p+dopant region;
forming an active gate region on said substrate adjacent said source region, copmprsing forming a first gate oxide region above said n-type substrate between said first and second p+dopant regions and forming a first polysilicon conductor region above said first gate oxide region; and
forming a first inactive gate region on said substrate in parallel to said active gate region, comprising forming a second gate oxide region above said n-type substrate adjacent said first p+dopant region, forming a second polysilicon conductor region above second first gate oxide region, and electrically coupling said second polysilicon conductor region to said first polysilicon conductor region, wherein said source region, said drain region, said active gate region, and said first inactive gate region comprise said transistor, and wherein said first inactive gate region is capable of dissipating at least a portion of a charge.

7. The method of claim 6 , further comprising:
forming a third p+dopant region on said n-type substrate adjacent said second gate oxide region;
forming a shallow trench isolation region adjacent said third p+dopant;
forming a n+dopant region on said n-type substrate adjacent said shallow trench isolation region; and
forming a third contact region above said n+dopant region.

8. The method of claim 7 , further comprising
coupling electrically a source pad to said source region;
coupling electrically a gate pad to said gate region; and
coupling electrically a drain pad to said drain region;
wherein said source, gate and drain pads are capable providing for testing of said transistor.

9. The method of claim 6 , wherein said first inactive gate region is further capable of at least partially dissipating said charge resulting from a plasma process.

10. The method of claim 6 , further comprising forming a second inactive gate region on said substrate in parallel to said first inactive gate, wherein said second inactive gate is capable of dissipating said at least a portion of said charge.

11. A method for forming a transistor, comprising:
forming a source region on a substrate;
forming an active gate region on said substrate adjacent said source region;
forming a drain region on said substrate adjacent said active gate region; and
determining an antenna ratio for said transistor and
forming a first inactive gate region in response to said antenna ratio on said substrate in parallel to said active gate region, wherein said source region, said drain region, said active gate region, and said first inactive gate region comprise said transistor; and said first inactive gate region is capable of dissipating at least a portion of a charge.

12. The integrated circuit device comprising:
a transistor, comprising:
a source region on a p-type substrate; wherein said source region comprises a first n+dopant region and first contact region above said first n+dopant region;
an active gate region on said substrate adjacent said source region, wherein said active gate region comprises a first gate oxide region formed between said first and second n+dopant regions and a first polysilicon conductor region above said first gate oxide region;
a drain region on said substrate adjacent said active gate region, wherein said drain region comprises a second n+dopant region and a second contact region above said second n+dopant region;
an inactive gate region on said substrate in parallel to said active gate region, wherein said inactive gate region is capable of dissipating at least a portion of a charge, said first inactive gate region comprises a second gate oxide region adjacent said first n+dopant region, a second polysilicon conductor region above second first gate oxide region, and said second polysilicon conductor region is electrically coupled to said first polysilicon conductor region.

13. The integrated circuit device of claim 12 , further comprising:
a third n+dopant region adjacent said second gate oxide region;
a shallow trench isolation region adjacent said third n+dopant;
a p+dopant region adjacent said shallow trench isolation region; and
a third contact region above said p+dopant region.

14. The integrated circuit device of claim 12 , further comprising
a source pad coupled electrically to said source region;
a gate pad coupled electrically to said gate region; and
a drain pad coupled electrically to said drain region;
wherein said source, gate and drain pads are capable providing for testing of said transistor.

15. The integrated circuit device of claim 12 , further comprising a plurality of inactive gates in parallel to said active gate, wherein the number inactive gates are based upon at least one of:
a

Assignees

• Globalfoundries Inc

Inventors

• Kerber Andreas
• Uppal Suresh
• Cimino Salvatore
• Jiang Hao

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title