Array substrate and display device

Patent metadata

Field	Value
Publication number	US-9324764-B2
Application number	US-201213806198-A
Country	US
Kind code	B2
Filing date	Aug 29, 2012
Priority date	Aug 29, 2011
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Embodiments of the present invention relate to an array substrate and a display device comprising the array substrate. According to an embodiment of the invention, there is provided an array substrate which comprises: a terminal region; and an active pixel region, the active pixel region comprising: a plurality of pixel units; a plurality of gate lines; a plurality of data lines; and a plurality of gate leading wires, wherein two columns of the plurality of pixel units are provided between two adjacent data lines among the plurality of data lines, each of the plurality of gate leading wires is disposed between the two columns of the plurality of pixel units, and each of the plurality of gate lines is connected to respective one of the plurality of gate leading wires.

First claim

What is claimed is:

1. An array substrate, comprising:
a terminal region; and
an active pixel region, the active pixel region comprising:
a plurality of pixel units;
a plurality of gate lines;
a plurality of data lines; and
a plurality of gate leading wires,
wherein two columns of the plurality of pixel units are provided between two adjacent data lines among the plurality of data lines, each of the plurality of gate leading wires is disposed between the two columns of the plurality of pixel units, and each of the plurality of gate lines is connected to respective one of the plurality of gate leading wires,
wherein two of the plurality of gate leading wires are provided between the two columns of the plurality of pixel units,
wherein the array substrate further comprises a dummy line, the dummy line is disposed between the two columns of the pixel units and is a leading wire not being connected to every gate line of the plurality of gate lines, the number of the dummy line disposed between the two columns of the pixel units is two,
the dummy line is floated.

2. The array substrate claimed as claim 1 , wherein the number of the plurality of gate lines is twice as many as the row number of the plurality of pixel units, and two of the gate lines are provided between two rows of pixel units among the plurality of pixel units.

3. The array substrate claimed as claim 1 , wherein the terminal region is located at one side or two opposed sides of the active pixel region, within the terminal region, there are provided a source driver and a gate driver, the plurality of data lines each are connected to the source driver, and the plurality of gate leading wires each are connected to the gate driver.

4. The array substrate claimed as claim 1 , wherein the terminal region is located at one side or two opposed sides of the active pixel region, within the terminal region, there is provided a source-gate integrated driver, the plurality of data lines and the plurality of gate leading wires each are connected to the source-gate integrated driver.

5. The array substrate claimed as claim 1 , wherein the plurality of gate leading wires and the plurality of data lines are located in the same layer, the plurality of gate leading wires are parallel to the plurality of data lines, each of the plurality of gate leading wires is electrically connected to respective one of the plurality of gate lines through a via hole.

6. The array substrate claimed as claim 1 , wherein the number of the plurality of gate lines is 640, the number of the plurality of data lines is 360, the number of the plurality of gate leading wires is 640, and respective two of the gate leading wires are disposed between the two columns of the pixel units of each of any 320 groups, each group having two columns of the pixel units.

7. The array substrate claimed as claim 6 , wherein respective two of the dummy lines are disposed between the two columns of the pixel units of each of remaining 40 groups.

8. The array substrate claimed as claim 1 , wherein the plurality of gate leading wires and the plurality of data lines are located in the different layers.

9. A display device, comprising:
an array substrate, including:
a terminal region; and
an active pixel region, the active pixel region comprising:
a plurality of pixel units;
a plurality of gate lines;
a plurality of data lines; and
a plurality of gate leading wires;
a color filter substrate, disposed opposite the array substrate; and
a liquid crystal layer, interposed between the array substrate and the color filter substrate,
wherein two columns of the plurality of pixel units are provided between two adjacent data lines among the plurality of data lines, each of the plurality of gate leading wires is disposed between the two columns of the plurality of pixel units, and each of the plurality of gate lines is connected to respective one of the plurality of gate leading wires,
wherein the array substrate further comprises a dummy line, the dummy line is disposed between the two columns of the pixel units and is a leading wire not being connected to every gate line of the plurality of gate lines, the number of dummy line disposed between the two columns of the pixel units is two,
wherein two of the plurality of gate leading wires are provided between the two columns of the plurality of pixel units, the dummy line is floated.

10. The display device claimed as claim 9 , wherein number of the plurality of gate lines is twice as many as the row number of the plurality of pixel units, and two of the gate lines are provided between two rows of pixel units among the plurality of pixel units.

11. The display device claimed as claim 9 , wherein the terminal region is located at one side or two opposed sides of the active pixel region, within the terminal region, there are provided a source driver and a gate driver, the plurality of data lines each are connected to the source driver, and the plurality of gate leading wires each are connected to the gate driver.

12. The display device claimed as claim 9 , wherein the terminal region is located at one side or two opposed sides of the active pixel region, within the terminal region, there is provided a source-gate integrated driver, the plurality of data lines and the plurality of gate leading wires each are connected to the source-gate integrated driver.

13. The display device claimed as claim 9 , wherein the plurality of gate leading wires and the plurality of data lines are located in the same layer, the plurality of gate leading wires are parallel to the plurality of data lines, each of the plurality of gate leading wires is electrically connected to respective one of the plurality of gate lines through a via hole.

14. The display device claimed as claim 9 , wherein the plurality of gate leading wires and the plurality of data lines are located in the different layers.

Assignees

• Wang Benlian
• Zhang Zhiqin
• Bai Feng
• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Wang Benlian
• Zhang Zhiqin
• Bai Feng

Classifications

• H10H29/142 Primary

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• G09G2310/0281

  Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure · CPC title

• G02F2001/13606

  Physics · mapped topic

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G02F2201/506

  Repairing, e.g. with redundant arrangement against defective part · CPC title