High mobility transistors

Patent metadata

Field	Value
Publication number	US-9324717-B2
Application number	US-201414573021-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 28, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

First claim

What is claimed is:

1. A method of forming an integrated circuit, comprising the steps:
providing a substrate comprising silicon, said substrate having a first region of a first conductivity type in an area for a first polarity finFET and having a second region of a second, opposite, conductivity type in an area for a second, opposite, polarity finFET;
forming a dielectric layer 50 nanometers to 100 nanometers thick over said substrate;
forming a first trench in said dielectric layer down to said substrate in said area for said first polarity finFET;
forming a first silicon-germanium buffer 1 nanometer to 5 nanometers thick on said substrate in said first trench;
forming a first polarity fin of said first polarity finFET on said first silicon-germanium buffer, so that said first polarity fin extends above a top surface of said dielectric layer;
forming an epitaxial blocking layer over said dielectric layer so as to cover said first polarity fin;
forming a second trench in said epitaxial blocking layer and said dielectric layer down to said substrate in said area for said second polarity finFET;
forming a second silicon-germanium buffer 1 nanometer to 5 nanometers thick on said substrate in said second trench;
forming a second polarity fin of said second polarity finFET on said second silicon-germanium buffer, so that said second polarity fin extends above a top surface of said dielectric layer;
forming a cap layer of dielectric material over said epitaxial blocking layer so as to cover said second polarity fin;
removing said cap layer and said epitaxial blocking layer by a chemical mechanical polish (CMP) process so as to planarize said first polarity fin and said second polarity fin down to said dielectric layer; and
recessing said dielectric layer so that said first polarity fin and said second polarity fin extend at least 10 nanometers above said dielectric layer.

2. The method of claim 1 , wherein:
said first silicon-germanium buffer is formed to have a germanium atomic fraction at said substrate of less than 20 percent and a germanium atomic fraction at a top surface of said first silicon-germanium buffer over 80 percent; and
said second silicon-germanium buffer is formed to have a germanium atomic fraction at said substrate of less than 20 percent and a germanium atomic fraction at a top surface of said second silicon-germanium buffer over 80 percent.

3. The method of claim 1 , wherein said first polarity fin comprises gallium arsenide.

4. The method of claim 1 , wherein said first polarity fin comprises indium gallium arsenide.

5. The method of claim 4 , wherein said first polarity fin has an indium to gallium ratio of 50:50 to 57:43.

6. The method of claim 1 , wherein said first polarity fin comprises indium phosphide.

7. The method of claim 1 , wherein said first polarity fin comprises germanium.

8. The method of claim 1 , wherein said second polarity fin comprises germanium.

Assignees

• Texas Instruments Inc

Inventors

• Niimi Hiroaki
• Mehrotra Manoj
• Wise Rick L

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193 Primary

  the components including FinFETs · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/124

  Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions · CPC title