Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9324657-B2
Application number	US-201414534607-A
Country	US
Kind code	B2
Filing date	Nov 6, 2014
Priority date	Nov 8, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Provided are semiconductor packages and methods of fabricating the same. The method may include, stacking a lower semiconductor chip on a lower package substrate, forming a lower molding layer on the lower package substrate, forming a connecting through-hole and an element through-hole by performing a laser drilling process on the lower molding layer, and stacking an upper package substrate having a bottom surface to which a passive element is bonded on the lower package substrate to insert the passive element into the element through-hole.

First claim

What is claimed is:

1. A semiconductor package comprising:
a lower package including a lower package substrate, a lower semiconductor chip stacked on the lower package substrate, and a lower molding layer covering the lower semiconductor chip on the lower package substrate and including an element through-hole; and
an upper package stacked on the lower package, the upper package including an upper package substrate, an upper semiconductor chip stacked on the upper package substrate, and a passive element bonded to a bottom surface of the upper package substrate,
wherein the passive element is inserted in the element through-hole.

2. The semiconductor package of claim 1 , wherein the lower molding layer further includes a connecting through-hole in which a conductive connection part is inserted,
wherein the conductive connection part electrically connects the lower package substrate to the upper package substrate, and
wherein the element through-hole is disposed between the lower semiconductor chip and the connecting through-hole.

3. The semiconductor package of claim 2 , wherein the element through-hole includes a plurality of element through-holes, and the passive element includes a plurality of passive elements inserted in the plurality of element through-holes, and
wherein the plurality of element through-holes are disposed at both sides of the lower semiconductor chip.

4. The semiconductor package of claim 2 , wherein the connecting through-holes includes a plurality of connecting through-holes, and the conductive connection part includes a plurality of conductive connection parts inserted in the plurality of connecting through-holes,
wherein the element through-hole is disposed between a first sidewall of the lower semiconductor chip and the conductive connection part adjacent to the first sidewall of the lower semiconductor chip, and
wherein a distance between the first sidewall of the lower semiconductor chip and the conductive connection part adjacent to the first sidewall of the lower semiconductor chip is greater than a distance between a second sidewall of the lower semiconductor chip and the conductive connection part adjacent to the second sidewall of the lower semiconductor chip.

5. The semiconductor package of claim 1 , wherein a bottom surface of the element through-hole is higher than a top surface of the lower package substrate.

6. The semiconductor package of claim 5 , further comprising:
a first element interconnection and a second element interconnection provided on the bottom surface of the upper package substrate,
wherein the first element interconnection and the second element interconnection are electrically connected to the passive element.

7. The semiconductor package of claim 1 , wherein the element through-hole exposes a top surface of the lower package substrate.

8. The semiconductor package of claim 7 , further comprising:
a first element interconnection disposed on the top surface of the lower package substrate and exposed by the element through-hole; and
a second element interconnection disposed on the bottom surface of the upper package substrate and facing the first element interconnection,
wherein one surface of the passive element is in contact with the first element interconnection, and another surface of the passive element is in contact with the second element interconnection.

9. The semiconductor package of claim 2 , wherein the conductive connection part is in contact with an inner sidewall of the connecting through-hole.

10. A semiconductor package comprising:
a lower package substrate;
a lower semiconductor chip mounted on the lower package substrate;
an upper package substrate stacked on the lower package substrate;
at least one upper semiconductor chip mounted on the upper package substrate; and
a passive element disposed on a bottom surface of the upper package substrate.

11. The semiconductor package of claim 10 , wherein the lower package substrate includes a lower molding layer in which a connecting through-hole and an element through-hole are formed,
wherein the passive element is inserted in the element through-hole, and
wherein a conductive connection part which electrically connects the lower package substrate to the upper package substrate is inserted in the connecting through-hole.

12. The semiconductor package of claim 11 , wherein the element through-hole includes a plurality of element through-holes, and the passive element includes a plurality of passive elements inserted in the plurality of element through-holes, and
wherein the connecting through-holes includes a plurality of connecting through-holes, and the conductive connection part includes a plurality of conductive connection parts inserted in the plurality of connecting through-holes.

13. The semiconductor package of claim 11 , wherein a bottom surface of the element through-hole is higher than a top surface of the lower package substrate.

14. The semiconductor package of claim 11 , wherein the element through-hole exposes a top surface of the lower package substrate.

Assignees

• Seo Jangmee
• Lee Heeseok
• Lee Jong-Won
• Samsung Electronics Co Ltd

Inventors

• Seo Jangmee
• Lee Heeseok
• Lee Jong-Won

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title