Chip thermistor and method of manufacturing same

US9324483B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9324483-B2
Application numberUS-201414514738-A
CountryUS
Kind codeB2
Filing dateOct 15, 2014
Priority dateJun 24, 2010
Publication dateApr 26, 2016
Grant dateApr 26, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A chip thermistor 1 has a thermistor portion 7 comprised of a ceramic material containing respective metal oxides of Mn, Ni, and Co as major ingredients; a pair of composite portions 9, 9 comprised of a composite material of Ag—Pd, and respective metal oxides of Mn, Ni, and Co and arranged on both sides of the thermistor portion 7 so as to sandwich in the thermistor portion 7 between the composite portions 9, 9 ; and external electrodes 5, 5 connected to the pair of composite portions 9, 9 , respectively. In this manner, the pair of composite portions 9, 9 are used as bulk electrodes and, for this reason, the resistance of the chip thermistor 1 can be adjusted mainly with consideration to the resistance in the thermistor portion 7 , without need for much consideration to the distance between the external electrodes 5, 5 and other factors.

First claim

Opening claim text (preview).

What is claimed is: 1. A chip thermistor comprising: a thermistor portion comprised of a ceramic material containing a metal oxide including at least one of Mn, Ni, or Co; a pair of composite portions comprised of a composite material including a metal and a metal oxide, the pair of composite portions being arranged on both sides of the thermistor portion so as to sandwich in the thermistor portion between the composite portions. 2. The chip thermistor according to claim 1 , wherein the thermistor portion is configured in a layered structure such that a direction in which the pair of composite portions are opposed to each other is a laminated direction. 3. The chip thermistor according to claim 1 , wherein each of the pair of composite portions is configured in a layered structure such that a direction in which the pair of composite portions are opposed to each other is a laminated direction. 4. The chip thermistor according to claim 1 , wherein the thermistor portion is substantially connected to the pair of composite portions, on both sides thereof. 5. The chip thermistor according to claim 1 , wherein the thermistor portion is composed of a thermistor element having a negative characteristic, and a thickness of the thermistor portion in a direction in which the pair of composite portions are opposed to each other, is any length in the range of 0.01 times a longitudinal length of the element body to 0.8 times the longitudinal length of the element body. 6. The chip thermistor according to claim 1 , wherein the composite material is a material in which the metal is dispersed in the metal oxide or in which the metal oxide is dispersed in the metal. 7. The chip thermistor according to claim 1 , wherein in each pair of composite portions, the metal in the composite material forms an electrical conduction path between an external and the thermistor portion. 8. The chip thermistor according to claim 1 , wherein an insulating layer is formed at least over a region across the thermistor portion out of an exterior surface of an element body which includes the thermistor portion and the pair of composite portions. 9. The chip thermistor according to claim 1 , wherein a thickness of the thermistor portion is controlled based on a number of identical thermistor layers laminated together. 10. The chip thermistor according to claim 1 , wherein a resistance of the chip thermistor is controlled based on a number of identical thermistor layers laminated together. 11. A method for manufacturing a chip thermistor, comprising: preparing thermistor layers comprised of a ceramic material containing a metal oxide of at least one of Mn, Ni, or Co; preparing composite layers comprised of a composite material including a metal and a metal oxide; laminating the thermistor layers and the composite layers to obtain a multilayer body such that a predetermined number of said thermistor layers are sandwiched in between the composite layers; cutting the multilayer body to obtain a plurality of element bodies. 12. The method for manufacturing a chip thermistor according to claim 11 , wherein a thickness of the thermistor layers is controlled based on a number of identical thermistor layers laminated together. 13. The method for manufacturing a chip thermistor according to claim 11 , where in a resistance of the chip thermistor is controlled based on a number of identical thermistor layers laminated together. 14. The method according to claim 11 , wherein the thermistor layers are composed of a thermistor element having a negative characteristic, and a thickness of the thermistor layers in a direction in which the composite layers are opposed to each other, is any length in the range of 0.01 times a longitudinal length of the element body to 0.8 times the longitudinal length of the element body.

Assignees

Inventors

Classifications

  • adapted for manufacturing resistor chips · CPC title

  • containing oxides or oxidic compounds, e.g. ferrites · CPC title

  • Terminals or electrodes formed on resistive elements having negative temperature coefficient · CPC title

  • Apparatus or processes specially adapted for manufacturing resistors (providing fillings for housings or enclosures H01C1/02; reducing insulation surrounding a resistor to powder H01C1/03; manufacture of thermally variable resistors H01C7/02, H01C7/04) · CPC title

  • Thermally variable · CPC title

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Frequently asked questions

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What does patent US9324483B2 cover?
A chip thermistor 1 has a thermistor portion 7 comprised of a ceramic material containing respective metal oxides of Mn, Ni, and Co as major ingredients; a pair of composite portions 9, 9 comprised of a composite material of Ag—Pd, and respective metal oxides of Mn, Ni, and Co and arranged on both sides of the thermistor portion 7 so as to sandwich in the thermistor portion 7 between …
Who is the assignee on this patent?
Tdk Corp
What technology area does this patent fall under?
Primary CPC classification H01C7/008. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).