NAND flash memory

Patent metadata

Field	Value
Publication number	US-9324450-B2
Application number	US-201313799215-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

First claim

The invention claimed is:

1. A method of operating a memory having a NAND flash memory array and a page buffer associated with the NAND flash memory array, comprising:
selecting a page of the NAND flash memory array;
storing data from the selected page in the page buffer;
performing ECC computations on the data in the page buffer;
outputting the data from the page buffer; and
repeating the page selecting, data storing, ECC computation performing, and data outputting steps so that data output is continuous across page boundaries and from logically contiguous memory locations without wait intervals;
wherein the page selecting step initially comprises selecting a default page in the NAND flash memory array, and subsequently comprises selecting successive sequential pages of the NAND flash memory array;
wherein the page selecting, data storing, and ECC computation performing steps are initially performed automatically during power-up of the flash memory, and are subsequently performed in response to a read command;
wherein the data outputting step is performed in response to the read command;
wherein the memory further comprises a power-up detector, the method further comprising initiating the initially performed page selecting step and the initially performed data storing step from the power-up detector during power-up of the memory; and
wherein the memory further comprises a buffer mode flag, the method further comprising setting the buffer mode flag into a continuous page read mode from the power-up detector upon power-up.

2. The method of claim 1 wherein the read command corresponds to a high-performance serial flash NOR (“HPSF-NOR”) read command and is clock-compatible therewith.

3. The method of claim 2 wherein the read command is one of a Read command 03h, a Fast Read command 0Bh, a Fast Read Dual Output command 3Bh, a Fast Read Quad Output command 6Bh, a Fast Read Dual I/O command BBh, or a Fast Read Quad I/O command EBh.

4. The method of claim 2 wherein time used for the data storing step and the ECC computation performing step is buried in time used for the data outputting step.

5. The method of claim 4 wherein the page selecting step is performed using bad block management.

6. The method of claim 1 wherein the memory further comprises a configurable single-bit and multiple-bit SPI interface, further comprising:
outputting the data from the page buffer to the configurable single-bit and multiple-bit SPI interface.

7. A method of powering up flash memory having a NAND flash memory array and a page buffer associated with the NAND flash memory array, comprising:
setting the flash memory in a continuous read mode or a buffer read mode;
transferring a page of data from a default page of the NAND flash memory array to the page buffer;
ECC processing the default page of data in the page buffer to provide an ECC processed default page of data;
after the data transferring step and the ECC processing step, receiving a read command; and
when the flash memory is in the continuous read mode, outputting from the flash memory in response to the read command receiving step, a continuous data output across page boundaries and from logically contiguous memory locations without wait intervals, beginning with the ECC processed default page of data in the page buffer; and
when the flash memory is in the buffer read mode, outputting from the flash memory in response to the read command receiving step, a data output limited to data in the page buffer;
wherein the flash memory comprises a power-up detector, the method further comprising initiating the transferring step from the power-up detector during power-up of the flash memory; and
wherein the flash memory further comprises a buffer mode flag and the setting step comprises setting the buffer mode flag into a continuous page read mode from the power-up detector upon power-up.

8. The method of claim 7 further comprising establishing the default page under a manufacturer's control.

9. The method of claim 7 further comprising establishing the default page under a user's control.

10. The method of claim 7 wherein the memory further comprises a configurable single-bit and multiple-bit SPI interface, further comprising:
outputting the continuous data output from the configurable single-bit and multiple-bit SPI interface.

11. A method of operating a NAND flash memory comprising:
selecting a default page of a NAND flash memory array of the NAND flash memory during power-up thereof;
storing data from the default page of the NAND flash memory array in a page buffer during power-up of the NAND flash memory;
performing ECC computations on the data stored in the page buffer after the storing step;
receiving a read command; and
providing, from the NAND flash memory via the page buffer and in response to the read command receiving step, a continuous data output across page boundaries and from logically contiguous memory locations without wait intervals;
wherein the NAND flash memory comprises a power-up detector and a buffer mode flag, the method further comprising:
initiating the default page selecting step and the data storing step from the power-up detector during power-up of the NAND flash memory; and
setting the buffer mode flag into a continuous page read mode from the power-up detector upon power-up.

12. The method of claim 11 further comprising outputting the continuous data output from the page buffer to a configurable single-bit and multiple-bit SPI interface.

Assignees

• Winbond Electronics Corp

Inventors

• Jigour Robin John
• Chen Hui
• Michael Oron

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C29/04 Primary

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title