Sense amplifiers and memory devices having the same

Patent metadata

Field	Value
Publication number	US-9324384-B2
Application number	US-201414504596-A
Country	US
Kind code	B2
Filing date	Oct 2, 2014
Priority date	Jan 17, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.

First claim

What is claimed is:

1. A sense amplifier, comprising:
a switching transistor configured to apply a ground voltage to a ground node in response to a sense enable signal;
a first detection circuit coupled between the ground node and a first detection node, the first detection circuit being configured to provide a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line;
a second detection circuit coupled between the ground node and a second detection node, the second detection circuit being configured to provide a second detection signal to the second detection node based on a voltage of a complementary bit-line;
a latch circuit connected to a supply voltage, the first detection node and the second detection node, the latch circuit being configured to,
generate a first amplified signal and a second amplified signal based on the first and second detection signals,
output the first amplified signal through a latch node, and

output the second amplified signal through a complementary latch node; and
wherein the mode signal has a first logic level in a double-ended read mode, and has a second logic level in a single-ended read mode, the first logic level being different from the second logic level.

2. The sense amplifier of claim 1 , wherein:
the first detection circuit includes,
a mode control transistor coupled between the ground node and the first detection node, the mode control transistor having a gate configured to receive the mode signal, and
at least one first transistor coupled between the ground node and the first detection node, the at least one first transistor having a gate connected to the bit-line; and

the second detection circuit includes,
a balance transistor coupled between the ground node and the second detection node, the balance transistor having a gate configured to receive the ground voltage, and
at least one second transistor coupled between the ground node and the second detection node, the at least one second transistor having a gate connected to the complementary bit-line.

3. The sense amplifier of claim 2 , wherein a current driving capability of the mode control transistor is the same or substantially the same as a current driving capability of the balance transistor.

4. The sense amplifier of claim 2 , wherein a sum of a current driving capability of the at least one first transistor is the same or substantially the same as a sum of a current driving capability of the at least one second transistor.

5. The sense amplifier of claim 2 , wherein a number of the at least one first transistors is the same as a number of the at least one second transistors.

6. The sense amplifier of claim 1 , wherein:
in the double-ended read mode, the first detection circuit is configured to receive a bit-line signal through the bit-line and the second detection circuit is configured to receive a complementary bit-line signal through the complementary bit-line; and
in the single-ended read mode, the first detection circuit is configured to receive the bit-line signal through the bit-line and the second detection circuit is configured to receive the supply voltage through the complementary bit-line.

7. The sense amplifier of claim 1 , wherein the latch circuit comprises:
a first latch transistor coupled between the supply voltage and the latch node, the first latch transistor having a gate connected to the complementary latch node;
a second latch transistor coupled between the supply voltage and the complementary latch node, the second latch transistor having a gate connected to the latch node;
a third latch transistor coupled between the latch node and the first detection node, the third latch transistor having a gate connected to the complementary latch node; and
a fourth latch transistor coupled between the complementary latch node and the second detection node, the fourth latch transistor including a gate connected to the latch node.

8. The sense amplifier of claim 1 , further comprising:
a reset circuit configured to reset a voltage of the latch node and a voltage of the complementary latch node to the supply voltage in response to the sense enable signal.

9. The sense amplifier of claim 8 , wherein the reset circuit comprises:
a first reset transistor coupled between the supply voltage and the latch node, the first reset transistor having a gate configured to receive the sense enable signal;
a second reset transistor coupled between the supply voltage and the complementary latch node, the second reset transistor having a gate configured to receive the sense enable signal; and
a third reset transistor coupled between the latch node and the complementary latch node, the third reset transistor having a gate configured to receive the sense enable signal.

10. The sense amplifier of claim 1 , further comprising:
a precharge circuit configured to precharge the bit-line and the complementary bit-line to the supply voltage in response to a first precharge signal and a second precharge signal.

11. The sense amplifier of claim 10 , wherein the precharge circuit comprises:
a first precharge transistor coupled between the supply voltage and the bit-line, the first precharge transistor having a gate configured to receive the first precharge signal;
a second precharge transistor coupled between the supply voltage and the complementary bit-line, the second precharge transistor having a gate configured to receive the second precharge signal; and
a third precharge transistor coupled between the bit-line and the complementary bit-line, the third precharge transistor having a gate configured to receive the first precharge signal.

12. The sense amplifier of claim 11 , wherein:
the first precharge signal and the second precharge signal have a same logic level as the sense enable signal when the mode signal has a first logic level;
the first precharge signal has a same logic level as the sense enable signal and the second precharge signal is maintained at the first logic level when the mode signal has a second logic level; and
the first logic level is different from the second logic level.

13. The sense amplifier of claim 1 , further comprising:
a first inverter configured to invert the first amplified signal;
a first transistor coupled between a global bit-line and the ground voltage, the first transistor having a gate connected to an output electrode of the first inverter;
a second inverter configured to invert the second amplified signal; and
a second transistor coupled between a global complementary bit-line and the ground voltage, the second transistor having a gate connected to an output electrode of the second inverter.

14. A memory device, comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns, the plurality of memory cells being connected to a plurality of word-lines, a plurality of bit-lines and a plurality of complementary bit-lines;
a plurality of sense amplifiers, each of the plurality of sense amplifiers being coupled to a corresponding column of the memory cell array through a corresponding bit-line and a corresponding complementary bit-line, and each of the plurality of sense amplifiers being configured to generate a first amplified signal and a second amplified signal based on a mode signal, a voltage of the corresponding bit-line and a voltage of the corresponding complementary bit-line;
a control circuit configured to generate the mode signal based on whether the plurality of memory cells are configured to perform a double-ended read operation or a single-ended read operation; and
wherein e

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Tae-Joong
• Park Sung-Hyun
• Rim Woo-Jin
• Yang Gi-Young

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title