Dynamically determining number of simulations required for characterizing intra-circuit incongruent variations

Patent metadata

Field	Value
Publication number	US-9323875-B2
Application number	US-201213406897-A
Country	US
Kind code	B2
Filing date	Feb 28, 2012
Priority date	Feb 28, 2012
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type of devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

First claim

What is claimed is:

1. A method comprising:
using a circuit recognition engine running on a computerized device, detecting dominant devices in an arc under consideration;
perturbing a device parameter value of each of said dominant devices, simulating said arc and making performance measurements to obtain a measure of sensitivity of said performance measurements to said perturbing said device parameter value of each of said dominant devices, using said computerized device;
calculating, using said computerized device, overall sensitivity of said arc using an equation

s
total

=

∑

i
∈
D

⁢

s
i
2

where s total is said overall sensitivity,
D comprises a set of said dominant devices, and
s i is a measure of sensitivity of said performance measurements to said perturbing said device parameter value of each of said dominant devices; and

calculating, using said computerized device, an estimate of sensitivity error using an equation comprising:

Error
=

s
total

-

s
total
2

+

(

S
v

-

∑

i
∈
D

⁢

sign
i

·

s
i

)

2

where S v is overall sensitivity of said arc when all device parameter values of all devices are perturbed simultaneously, and sign i is an estimated positive or negative sign of s i based on direction of perturbation.

2. The method of claim 1 , further comprising:
before perturbing each of said dominant devices, simulating said arc at nominal condition and making performance measurements to obtain a baseline performance of said arc, using said computerized device.

3. The method of claim 1 , each dominant device comprising at least one of
an on path device comprising a device on said arc that switches from non-conducting state to conducting state,
a switching device comprising a device whose gate connects to a transitioning signal, and
an off path device comprising a device on said arc that switches from conducting state to non-conducting state.

4. The method of claim 1 , said sign i being determined by at least one of
obtained from historical data,
obtained using a traditional or conservative method for a particular setting of slew, load, voltage, and temperature, and
obtained analytically by circuit recognition.

5. A method comprising:
using a circuit recognition engine running on a computerized device to detect a total of devices in an integrated circuit under consideration;
sorting said total of devices into a queue according to importance of each device in said integrated circuit, using said computerized device;
selecting a first device d from said queue and adding said first device d to set D, using said computerized device;
perturbing a device parameter value of said first device d, using said computerized device;
simulating said integrated circuit and making performance measurements to obtain a measure of sensitivity s d of said performance measurements to said perturbing said device parameter value of said first device d, using said computerized device;
calculating overall sensitivity of said integrated circuit using an equation

s
total

=

∑

d
∈
D

⁢

s
d
2

where D comprises a set of devices selected from said queue, using said computerized device;
using a verification equation to determine an error value, using said computerized device, said verification equation comprising:

Error
=

s
total

-

s
total
2

+

(

S
v

-

∑

i
∈
D

⁢

sign
i

·

s
i

)

2

where S v is overall sensitivity of an arc when all device parameter values of all devices are perturbed simultaneously, sign i is an estimated positive or negative sign of s i based on direction of perturbation and s i equals s d ; and
selecting a next device in said queue and testing as necessary until said error value is smaller than a predetermine

Assignees

• Habitz Peter A
• Joshi Amol A
• Singhee Amith
• Sundquist James E
• Zhang Wangyang
• Globalfoundries Inc

Inventors

• Habitz Peter A
• Joshi Amol A
• Singhee Amith
• Sundquist James E
• Zhang Wangyang

Classifications

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F2111/08

  Probabilistic or stochastic CAD · CPC title