Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory

Patent metadata

Field	Value
Publication number	US-9323688-B2
Application number	US-201514937330-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Oct 21, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A data access system including a storage device and a processor, which includes one or more levels of cache (LOC). In response to data required by the processor not being within the LOC, the processor generates a physical address to be accessed within the storage device in order to retrieve the data. The storage device includes a main memory and a cache module, which is configured as a final level of cache (FLOC) to be accessed by the processor prior to accessing the main memory. The cache module includes a controller that, in response to the data not being cached within the LOC, converts the physical address into a virtual address within the FLOC. The FLOC uses the virtual address to determine whether the data is within the FLOC. If the data is not within the FLOC, the cache module or the processor retrieves the data from the main memory.

First claim

What is claimed is:

1. A data access system comprising:
a storage device configured to store data; and
a processor including one or more levels of cache, wherein in response to data required by the processor not being cached within the one or more levels of cache, the processor is configured to generate a physical address to be accessed within the storage device in order to retrieve the data required by the processor,
wherein the storage device includes
(i) a main memory, and
(ii) a cache module configured as a final level of cache to be accessed by the processor prior to the processor accessing the main memory, wherein the cache module includes
a first controller configured to, in response to the data required by the processor not being cached within the one or more levels of cache of the processor, convert the physical address to be accessed within the storage device into a virtual address within the final level of cache,

wherein the final level of cache is configured to use the virtual address within the final level of cache to determine whether the data required by the processor is cached within the final level of cache, and
wherein, in response to the data required by the processor not being cached within the final level of cache, one or more of the cache module or the processor is configured to retrieve the data required by the processor from the main memory.

2. The data access system of claim 1 , wherein:
the cache includes dynamic random access memory;
the cache module further comprises a second controller; and
the second controller is configured to (i) convert the virtual address within the final level of cache into a physical address within the dynamic random access memory, and (ii) determine whether the data required by the processor is cached within the dynamic random access memory based on the physical address within the dynamic random access memory,
wherein in response to the data required by the processor being cached within the dynamic random access memory, the data required by the processor is determined to be cached within the final level of cache.

3. The data access system of claim 2 , wherein:
the second controller is configured to, in response to the data required by the processor being cached in the dynamic random access memory, access a location in the dynamic random access memory corresponding to the physical address within the dynamic random access memory; and
the first controller is configured to, in response to the data required by the processor not being cached in the dynamic random access memory, access a location in the main memory corresponding to the physical address within the dynamic random access memory.

4. The data access system of claim 2 , wherein the cache module is configured to access a second dynamic random access memory, and wherein the second controller is configured to:
convert the virtual address within the final level of cache into a physical address within the second dynamic random access memory; and
determine whether the data required by the processor is cached within the second dynamic random access memory based on the physical address within the second dynamic random access memory.

5. The data access system of claim 4 , wherein the second dynamic random access memory is located in a different system-on-chip (SOC) than the cache module.

6. The data access system of claim 1 , wherein the first controller is configured to perform a full set associative translation of the physical address to be accessed by the storage device to generate the virtual address.

7. The data access system of claim 1 , wherein the first controller is configured to:
without receiving a request for upcoming data from the processor, (i) predict that the processor is to request access to the upcoming data, (ii) access the upcoming data in the main memory, (iii) store the upcoming data in the cache of the cache module; and
subsequent to storing the upcoming data in the cache of the cache module, (i) receive a request for the upcoming data from the processor, and (ii) transfer the upcoming data from the cache of the cache module to the processor.

8. The data access system of claim 1 , wherein the main memory comprises a solid-state drive (SSD), and wherein the final level of cache comprises a dynamic random access memory (DRAM).

9. A network device comprising the data access system of claim 1 .

10. The network device of claim 9 , wherein the network device comprises at least one of a mobile phone, a tablet, or a computer.

11. The network device of claim 10 , further comprising a system bus connected between (i) the processor and (ii) the cache module and the main memory,
wherein the data is transferred (i) between the processor and the cache module via the system bus, and (ii) between the cache module and the main memory via the system bus.

12. A method of operating a data access system, wherein the data access system comprises (i) a processor having one or more levels of cache, and (ii) a storage system comprising a cache module and a main memory, wherein the cache module comprises a cache and a first controller, wherein the cache of the cache module is configured as a final level of cache to be accessed by the cache module prior to the cache module accessing the main memory, the method comprising:
determining whether data required by the processor is cached within the one or more levels of cache of the processor;
if the data required by the processor is not cached within the one or more levels of cache of the processor, (i) generating a physical address, via the processor, to be accessed within the storage system in order to retrieve the data required by the processor; and
at the first controller and in response to the data required by the processor not being cached within the one or more levels of cache of the processor, converting the physical address to be accessed within the storage system into a virtual address within the final level of cache to determine whether the data required by the processor is cached within the final level of cache,
wherein, in response to the data required by the processor not being cached within the final level of cache, retrieving the data required by the processor from the main memory.

13. The method of claim 12 , further comprising, at a second controller in the cache module:
converting the virtual address within the final level of cache into a physical address within a dynamic random access memory, wherein the cache includes the dynamic random access memory;
determining whether the data required by the processor is cached within the dynamic random access memory based on the physical address within the dynamic random access memory; and
in response to the data required by the processor being cached within the dynamic random access memory, determining the data required by the processor to be cached within the final level of cache.

14. The method of claim 13 , further comprising:
at the second controller and in response to the data required by the processor being cached in the dynamic random access memory, accessing a location in the dynamic random access memory corresponding to the physical address within the dynamic random access memory; and
at the first controller and in response to the data required by the processor not being cached in the dynamic random access memory, accessing a location in the main memory corresponding to the physical address within the dynamic random access memory.

15. The method of claim 12 , further comprising at the first controller performing a full set associative translation of the physical address to

Assignees

• Marvell World Trade Ltd

Inventors

• Sutardja Sehat

Classifications

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F3/0638

  Organizing or formatting or addressing of data · CPC title

• G06F12/10

  Address translation · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title