Identifying and prioritizing critical instructions within processor circuitry

Patent metadata

Field	Value
Publication number	US-9323678-B2
Application number	US-201113993376-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

In one embodiment, the present invention includes a method for identifying a memory request corresponding to a load instruction as a critical transaction if an instruction pointer of the load instruction is present in a critical instruction table associated with a processor core, sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction, and prioritizing the memory request ahead of other pending transactions responsive to the critical indicator. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores including a first core to execute instructions, the first core including a pipeline having a reorder buffer (ROB) including a plurality of entries each associated with an instruction received in the pipeline, and a first logic to determine whether a load instruction is a critical instruction based at least in part on a miss indicator of an entry of the ROB associated with the load instruction to indicate that the load instruction missed in a core cache and a dependency counter field of the entry of the ROB that is greater than a threshold, and if so to send a memory request transaction associated with the load instruction to a system agent of the processor with a critical indicator to indicate the critical instruction; and
the system agent coupled to the first core and including a distributed cache controller having a plurality of portions each associated with a corresponding portion of a distributed shared cache memory of the system agent, each of the distributed cache controller portions and the distributed shared cache memory portions associated with one of the plurality of cores, a memory controller to interface with a system memory coupled to the processor and an interconnect to couple the distributed shared cache memory and the distributed cache controller with the first core, wherein the system agent is to prioritize the memory request transaction based on the critical indicator at a plurality of points of the system agent.

2. The processor of claim 1 , wherein the system agent comprises a first arbiter associated with the interconnect, the first arbiter to prioritize the memory request transaction including the critical indicator ahead of at least one other transaction present in a buffer to store pending transactions for insertion onto the interconnect.

3. The processor of claim 2 , wherein the system agent comprises a second arbiter associated with the distributed cache controller, the second arbiter to prioritize the memory request transaction including the critical indicator ahead of at least one other transaction that seeks access to the distributed shared cache memory.

4. The processor of claim 3 , wherein the system agent comprises a third arbiter associated with the memory controller, the third arbiter to prioritize the memory request transaction including the critical indicator ahead of at least one other transaction that seeks access to the system memory.

5. The processor of claim 1 , wherein the distributed shared cache memory is to store a table having plurality of entries each to store an instruction pointer for a critical instruction, the first logic to insert an instruction pointer of the load instruction in an entry of the table when the load instruction is identified as a critical instruction.

6. The processor of claim 5 , wherein the first logic is to access the critical instruction table to determine whether a second load instruction is a critical instruction and to identify the second load instruction as a critical instruction if an entry of the table is associated with the second load instruction.

7. The processor of claim 1 , wherein the first logic is to set the miss indicator of the ROB entry when the data associated with the load instruction is not present in a first and a second cache of the first core.

8. The processor of claim 1 , wherein the system agent is to prioritize a second transaction over at least one other pending transaction based on an identification of an originating core of the processor.

9. The processor of claim 8 , wherein the system agent is to prioritize the second transaction corresponding to a latency-sensitive request from the first core over a third transaction corresponding to a bandwidth-sensitive request from a graphics engine of the processor.

10. A method comprising:
identifying, in a first core of a processor, a memory request corresponding to a load instruction as a critical transaction and storing an instruction pointer and metadata associated with the load instruction in a first table of the first core if a dependency counter field of an entry of a reorder buffer (ROB) associated with the load instruction is greater than a threshold and a miss indicator of the ROB entry is set, the miss indicator to indicate that the load instruction missed in a core cache;
thereafter identifying the load instruction as a critical instruction if the instruction pointer of the load instruction is present in the first table of the first core;
sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction, responsive to the presence of the instruction pointer in the first table; and
prioritizing the memory request ahead of a plurality of pending transactions in the system agent responsive to the critical indicator.

11. The method of claim 10 , further comprising prioritizing the memory request onto an interconnect of the system agent ahead of at least one other transaction seeking access to the interconnect.

12. The method of claim 11 , further comprising prioritizing lookup for the memory request in a shared cache memory of the system agent ahead of at least one other transaction seeking access to the shared cache memory.

13. The method of claim 12 , further comprising:
prioritizing a communication associated with the memory request from a memory controller of the system agent to a system memory coupled to the processor to obtain data for the memory request ahead of at least one other transaction seeking access to the system memory; and
prioritizing return of the data to the first core ahead of at least one other transaction seeking to communicate with the first core.

14. The method of claim 10 , further comprising not storing the instruction pointer and the metadata in the first table if a ratio of a number of load instructions stored in the first table to a total number of unique load instructions is greater than a ratio threshold.

15. A system comprising:
a multicore processor including a first core to execute instructions, the first core including a pipeline, a first cache memory and a first logic to identify an instruction as a critical instruction based on a criticality level and a delinquency level associated with the instruction, including to identify the instruction as the critical instruction when a metadata field of a reorder buffer (ROB) entry associated with the instruction is greater than a first threshold and the instruction misses in at least one cache memory of the first core, the multicore processor further including and a system agent including a cache controller to control access to a shared cache memory and a memory controller to interface with a dynamic random access memory (DRAM) coupled to the multicore processor, wherein the cache controller and the memory controller are to prioritize fulfillment of a memory request having a critical indicator ahead of at least one other memory request not having the critical indicator; and
the DRAM coupled to the multicore processor.

16. The system of claim 15 , wherein the system agent comprises a first arbiter associated with an interconnect of the system agent to prioritize the memory request having the critical indicator, a second arbiter associated with the cache controller to prioritize the memory request having the critical indicator and a third arbiter associated with the memory controller to prioritize the memory request having the critical indicator.

17. The system of claim 15 , wherein the first logic is to store an in

Assignees

• Kumar Amit
• Subramoney Sreenivas
• Intel Corp

Inventors

• Kumar Amit
• Subramoney Sreenivas

Classifications

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title

• G06F9/3824 Primary

  Operand accessing · CPC title

• G06F9/3857

  Physics · mapped topic