Methods for reducing energy consumption of buffered applications using simultaneous multi-threading processor

Patent metadata

Field	Value
Publication number	US-9323571-B2
Application number	US-77417804-A
Country	US
Kind code	B2
Filing date	Feb 6, 2004
Priority date	Feb 6, 2004
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A state of an application running in a system is monitored. The monitoring of the application states includes monitoring one or more buffers associated with the application. Dispatch of one or more threads in the system is controlled. At least one thread in the system is associated with the application. Resources in the system are managed based at least on the state of the application and the state of the one or more threads in the system.

First claim

What is claimed is:

1. A method, comprising:
monitoring a state of a multi-threaded application running in a system and a buffer associated with the multi-threaded application, wherein each thread includes one or more activities to be executed by the system;
determining availability of a processor to perform simultaneous multi-threading and the buffer;
coordinating dispatch of threads of the multi-threaded application to increase execution overlap of activities executing in the system based, at least in part, on the availability of the buffer;
dynamically adjusting one or more of a frequency or a voltage applied to the processor based, at least in part, on the availability of the buffer and the coordination of the dispatch of the threads; and
dynamically adjusting the buffer size based, at least in part, on the adjusted voltage or frequency applied to the processor and the coordination of the dispatch of the threads.

2. The method of claim 1 , wherein coordinating dispatch of the threads of the multi-threaded application includes assessing execution readiness of the one or more activities of each thread.

3. The method of claim 2 , wherein coordinating dispatch of the threads of the multi-threaded application includes delaying a ready-to-be-dispatched activity from being dispatched.

4. The method of claim 3 , wherein a first activity is delayed from being dispatched to wait for a second activity to be ready so that both the first and second activities are dispatched together, and wherein the first and second activities are from one or more applications.

5. The method of claim 1 , further comprising
determining the availability of configurable hardware components including an arithmetic logic unit (ALU), and registers in the system, wherein coordinating dispatch of the threads of the multi-threaded application is further based on the availability of the configurable hardware components.

6. The method of claim 5 , wherein adjusting the voltage applied to the processor includes powering on or powering off at least a portion of circuitry in the system.

7. The method of claim 1 , wherein monitoring the buffer associated with the multi-threaded application includes monitoring buffer fullness levels of the buffer.

8. The method of claim 7 , wherein monitoring the buffer fullness levels includes comparing the buffer level with predetermined buffer fullness levels, wherein the predetermined buffer fullness levels include a high level mark and a low level mark.

9. The method of claim 8 , wherein comparing the buffer level includes determining buffer overflow and buffer underflow conditions based, at least in part, on the high level mark and the low level mark.

10. A non-transitory computer readable storage medium containing executable instructions which, when executed in a processing system, causes the processing system to perform a method comprising:
monitoring a state of a multi-threaded application running in the processing system and a buffer associated with the multi-threaded application, wherein each thread includes one or more activities to be executed by the processing system;
determining availability of a processor to perform simultaneous multi-threading and the buffer;
coordinating dispatch of threads of the multi-threaded application to increase execution overlap of activities executing in the system based, at least in part, on the availability of the buffer;
dynamically adjusting one or more of a frequency or a voltage applied to the processor based, at least in part, on the availability of the buffer and the coordination of the dispatch of the threads; and
dynamically adjusting the buffer size based, at least in part, on the adjusted voltage or frequency applied to the processor and the coordination of the dispatch of the threads.

11. The computer readable storage medium of claim 10 , wherein coordinating dispatch of the threads of the multi-threaded application includes delaying a ready-to-be-dispatched activity from being dispatched.

12. The computer readable storage medium of claim 10 ,
wherein monitoring the buffer associated with the multi-threaded application includes monitoring buffer fullness levels of the buffer, and wherein monitoring the buffer fullness levels includes comparing the buffer level with predetermined buffer fullness levels, wherein the predetermined buffer fullness levels include a high level mark and a low level mark.

13. A system, comprising:
a memory to store data and instructions;
a processor coupled to said memory on a bus, said processor operable to perform instructions, said processor to include a bus unit to receive a sequence of instructions from said memory;
an execution unit coupled to said bus unit, said execution unit to execute said sequence of instructions, said sequence of instructions to cause said execution unit to:
monitor a state of a multi-threaded application running in the system and a buffer associated with the multi-threaded application, wherein each thread includes one or more activities to be executed by the system;
determine availability of a processor to perform simultaneous multi-threading and the buffer;
coordinate dispatch of threads of the multi-threaded application to increase execution overlap of activities executing in the system based, at least in part, on the availability of the buffer;
dynamically adjust one or more of a frequency or a voltage applied to the processor based, at least in part, on the availability of the buffer and the coordination of the dispatch of the threads; and
dynamically adjust the buffer size based, at least in part, on the adjusted voltage or frequency applied to the processor and the coordination of the dispatch of the threads.

14. The system of claim 13 , wherein said coordinating dispatch of the threads of the multi-threaded application includes delaying a ready-to-be-dispatched activity from being dispatched.

Assignees

• Yeung Minerva M
• Chen Yen-Kuang
• Intel Corp

Inventors

• Yeung Minerva M
• Chen Yen-Kuang

Classifications

• Y02B60/32

  Cross-Sectional Technologies · mapped topic

• G06F9/50 Primary

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title