Virtual machine and/or multi-level scheduling support on systems with asymmetric processor cores

Patent metadata

Field	Value
Publication number	US-9323547-B2
Application number	US-201313857305-A
Country	US
Kind code	B2
Filing date	Apr 5, 2013
Priority date	Oct 1, 2010
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Different processor cores in a computing device can support different features. In one or more embodiments, the features supported by each of multiple physical processor cores of a computing device are identified. A set of one or more features of the multiple physical processor cores to make available to virtual processor cores of the virtual machine are determined based at least in part on both the one or more features supported by each of the multiple physical processor cores and a number of virtual processor cores of the virtual machine. In additional embodiments, a multi-level scheduling model is used. An operating system level scheduler of an operating system schedules multiple applications for execution on multiple processor cores, and a user level scheduler of an application schedules application threads of that application for execution on one or more of the multiple processor cores.

First claim

What is claimed is:

1. A method in a computing device, the method comprising:
receiving, from a physical processor core on which a thread is scheduled, an undefined opcode exception indicating that that physical processor core does not support an instruction that caused the undefined opcode exception;
identifying the instruction that caused the undefined opcode exception;
selecting a second physical processor core which supports the instruction; and
scheduling the thread to run on the second physical processor core starting at the identified instruction that caused the undefined opcode exception, the second physical processor core supporting functionality which supports the identified instruction.

2. The method as recited in claim 1 , further comprising providing the identified instruction that caused the undefined opcode exception to an operating system of the computing device if the instruction is not supported by the one or more physical processor cores.

3. The method as recited in claim 1 , wherein scheduling the thread to run on the second physical processor core comprises scheduling a virtual processor core on the second physical processor core that supports the identified instruction that caused the undefined opcode exception.

4. The method as recited in claim 1 , further comprising, responsive to the scheduling, causing the thread to run on the second physical processor core starting at the identified instruction that caused the undefined opcode exception.

5. The method as recited in claim 1 , further comprising determining a set of features of the second physical processor core to make available to a virtual processor core of a virtual machine associated with the second physical processor core.

6. The method as recited in claim 5 , further comprising, responsive to the determining, making the set of features of the second physical processor core available to the virtual processor core of the virtual machine.

7. A method in a computing device, the method comprising:
responsive to determining that a number of features for execution by a particular processor core from among multiple processor cores exceeds a number of features capable of being executed by the particular processor core without causing an undefined opcode exception indicating that a physical processor core does not support an instruction that causes the undefined opcode exception:
identifying, for each of multiple processor cores of the computing device, one or more features supported by the processor core, the one or more features including functionality supported by a physical processor core of the processor core;
scheduling, by an operating system level scheduler of an operating system of the computing device, multiple applications for execution on the multiple processor cores; and
scheduling, by a user level scheduler of one application of the multiple applications and based at least in part on the one or more features supported by the physical processor cores of the multiple processor cores, application threads of the one application for execution on one or more of the multiple processor cores, the application thread being derived from a user mode scheduled application thread.

8. The method as recited in claim 7 , wherein the identifying further comprises identifying one or more feature properties associated with each of the one or more features, and wherein the scheduling application threads further comprises scheduling user mode scheduled application threads of the application based at least in part on the one or more feature properties associated with each of the one or more features.

9. The method as recited in claim 7 , further comprising scheduling application threads that execute in a user mode on a first set of processor cores of the multiple processor cores, and scheduling operating system functionality that executes in a kernel mode on a second set of processor cores of the multiple processor cores, wherein the first set of processor cores and the second set of processor cores include different ones of the multiple processor cores.

10. The method as recited in claim 7 , wherein the scheduling by the user level scheduler is further based at least in part on one or more memory access features that abstract a memory topology used by the computing device from the one application.

11. The method as recited in claim 7 , further comprising maintaining a record of both the features supported by the multiple processor cores and one or more feature properties associated with one or more of the features supported by the multiple processor cores.

12. The method as recited in claim 7 , wherein the multiple processor cores comprise multiple virtual processor cores of a virtual machine of the computing device.

13. The method as recited in claim 7 , wherein the multiple processor cores comprise multiple physical processor cores of the computing device.

14. The method as recited in claim 7 , wherein a first portion of the user mode scheduled application thread includes the application thread and a second portion of the user mode scheduled application thread includes a kernel thread.

15. The method as recited in claim 14 , wherein the scheduling by the operating system level scheduler is based at least in part on the kernel thread included in the second portion of the user mode scheduled application thread.

16. The method as recited in claim 7 , wherein the scheduling by the operating system level scheduler is based at least in part on a portion of the user mode scheduled application thread.

17. The method as recited in claim 7 , wherein the operating level scheduler and the user level scheduler each make use of a user mode scheduled application thread, the user mode scheduled application thread being a single thread that includes a kernel thread and an application thread.

18. A system comprising:
one or more processors; and
memory storing instructions which, when executed by the one or more processors, configure the one or more processors to perform acts comprising:
identifying, for each of multiple physical processor cores of the computing device, one or more features supported by the physical processor core, the one or more features including functionality supported by the physical processor core as opposed to causing an undefined opcode exception indicating that the physical processor core does not support an instruction that causes the undefined opcode exception;
scheduling, by an operating system level scheduler of an operating system of the computing device, multiple applications for execution on the multiple physical processor cores; and
scheduling, by a user level scheduler of one application of the multiple applications and based at least in part on the one or more features supported by the multiple physical processor cores, application threads of the one application for execution on one or more of the multiple physical processor cores, the application thread being derived from a user mode scheduled application thread.

19. The system as recited in claim 18 , wherein the operating level scheduler and the user level scheduler each make use of a user model scheduled application thread, the user mode scheduled application thread being a single thread that includes a kernel thread and an application thread.

20. The system as recited in claim 18 , further comprising scheduling application threads that execute in a user mode on a first set of processor cores of the multiple physical processor cores, and scheduling operating system functionality t

Assignees

• Microsoft Corp
• Microsoft Technology Licensing Llc

Inventors

• Jayamohan Ajith

Classifications

• G06F9/5044 Primary

  considering hardware capabilities · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F9/5088

  involving task migration · CPC title

• G06F2009/4557

  Distribution of virtual machine instances; Migration and load balancing · CPC title