Integrated circuit with internal and external voltage regulators

Patent metadata

Field	Value
Publication number	US-9323272-B2
Application number	US-201414318699-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
an internal voltage regulator for generating an internal voltage;
a digital core logic circuit that receives power from one of the internal voltage regulator and an external voltage regulator located outside of the integrated circuit;
a power on reset (POR) pin;
a test pin; and
a regulator selection circuit that receives an external power on reset (POR_EXT) signal from the POR pin and a TEST signal from the test pin and decodes the POR_EXT signal and the TEST signal to select one of the internal voltage regulator and the external voltage regulator to supply power to the digital core logic circuit,
wherein the integrated circuit is operable in:
(i) a first functional mode in which the integrated circuit uses the internal voltage supplied by the internal voltage regulator;
(ii) a second functional mode in which the integrated circuits uses an external voltage supplied by the external voltage regulator; and
(iii) a test mode in which the integrated circuits uses power supplied from one of the external voltage regulator and a test equipment voltage source.

2. The integrated circuit of claim 1 , wherein an external ballast is coupled to the internal voltage regulator for managing power provided to the integrated circuit in the first functional mode.

3. The integrated circuit of claim 1 , wherein:
the first functional mode provides a first power up sequence controlled by an internal power-on-reset (POR_INT) signal;
the second functional mode provides a second power up sequence controlled by the POR_INT signal and the POR_EXT signal; and
the test mode provides a third power up sequence controlled by the POR_EXT signal,
wherein one of the first, second and third power up sequences is used to select one of the internal voltage regulator and the external voltage regulator to supply power to the digital core logic circuit.

4. The integrated circuit of claim 3 , wherein the regulator selection circuit further comprises:
a first logic gate that receives the POR_INT and POR_EXT signals;
a selector having a first data input connected to an output of the first logic gate, a second data input that receives the POR_EXT signal, and a select input that receives the TEST signal, wherein the selector outputs a power on reset control (POR_CTRL) signal;
a first latch circuit having a data input tied to a first power supply voltage, a clock input that receives a low voltage detection signal of the first power supply voltage (LVD) and a reset input that receives a power on indicator signal (POR);
a second logic gate having a first data input, a second data input coupled to an output (Q) of the first latch circuit, and an output that provides a regulator power down (REG_PD) signal;
a first level shifter having a data input that receives a test control unit regulator power down (TCU_REG_PD) signal and a control input that receives the POR_CTRL signal from the selector;
a third logic gate having a first data input, a second data input coupled to an output of the first level shifter, and an output coupled to the first data input of the second logic gate;
a fourth logic gate having first and second data inputs, and an output coupled to the first data input of the third logic gate;
a second level shifter having a data input, a control input that receives the POR_CTRL signal, and an output connected to the first data input of the fourth logic gate;
a fifth logic gate having an output coupled to the second data input of the fourth logic gate, a first data input that receives the POR_EXT signal, and a second data input that receives the TEST signal; and
a sixth logic gate having an output coupled to the data input of the second level shifter, a first data input that receives a Fuse/Flash power down (PD) bit signal, and a second data input that receives an internal regulator power down (REG_PD_CORE) signal,
wherein the first and second level shifters are reset by the POR_CTRL signal when one of the POR_INT and POR_EXT signals is at a logic low state, and
wherein the POR_CTRL signal and the internal regulator power down (REG_PD_CORE) signal are used to select the one of the internal voltage regulator and the external voltage regulator for the first, second and third power up sequences.

5. The integrated circuit of claim 3 , wherein the regulator selection circuit further comprises:
a first logic gate that receives the POR_INT signal and the POR_EXT signal;
a selector having a first data input connected to an output of the first logic gate, a second data input that receives the POR_EXT signal, and a select input that receives the TEST signal, wherein the selector outputs a POR_CTRL signal;
a first latch circuit having a data input tied to a first power supply voltage, a clock input that receives a low voltage detection (LVD) signal of the first power supply voltage and a reset input that receives a power on reset signal (POR);
a second logic gate having a first data input, a second data input coupled to an output (Q) of the first latch circuit, and an output that provides an internal regulator power down (REG_PD) signal;
a first level shifter having a data input that receives a test control unit regulator power down (TCU_REG_PD) signal and a control input that receives the POR_CTRL signal from the selector;
a third logic gate having a first data input, a second data input coupled to an output of the first level shifter, and an output coupled to the first data input of the second logic gate;
a second latch circuit having a data input that receives the POR_EXT signal, a clock input that receives the LVD signal, and a reset input that receives the POR signal;
a second level shifter having a data input that receives an internal regulator power down (REG_PD_CORE) signal and a control input that receives the POR_CTRL signal from the selector; and
a fourth logic gate having a first data input coupled to an output of the second level shifter, a second data input coupled to the test pin for receiving the TEST signal, a third data input that receives the output (Q) of the second latch circuit, and an output coupled to the first data input of the third logic gate,
wherein the output (Q) of the second latch circuit turns the internal voltage regulator OFF in the second functional mode after a low-to-high transition on the POR_EXT signal, and
wherein the POR_CTRL and REG_PD signals are used to select the one of the internal voltage regulator and the external voltage regulator for the first, second and third power up sequences.

6. The integrated circuit of claim 3 , wherein the regulator selection circuit further comprises:
a first logic gate having a first input that receives an external regulator (EXT_REG) signal, a second input that receives the POR_EXT signal, and an output;
a second logic gate having a first input that receives the POR_INT signal, a second input coupled to the output of the first logic gate, and an output;
a selector having a first data input connected to the output of the second logic gate, a second data input that receives the POR_EXT signal, a select input that receives the TEST signal, and an output that provides a POR_CTRL signal;
a first latch circuit having a data input tied to a first power supply voltage (3.3V), a clock input receiving a low voltage detection (LVD) signal of the first power supply voltage and a reset input receiving a power on reset signal (POR);
a third logic gate having a first data input, a second data input coupled to an output (Q) of the first latch circuit, and an output that provides a regulator power down (REG_PD) signal;
a first level shifter having a data input that receives a test control unit regulator power down (TCU_REG_PD) signal and a control input that receives the POR_

Assignees

• Rana Manmohan
• Pandey Rakesh
• Thakur Nishant Singh
• Freescale Semiconductor Inc

Inventors

• Rana Manmohan
• Pandey Rakesh
• Thakur Nishant Singh

Classifications

• H03K3/3562

  of the primary-secondary type · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• G05F3/16 Primary

  being semiconductor devices · CPC title