Method and implementation for eliminating random pulse during power up of digital signal controller

Patent metadata

Field	Value
Publication number	US-9323267-B2
Application number	US-201313829972-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Mar 14, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A switching mode power converter includes a DSC with a digital PWM module configured for complementary operation mode during normal operation. The control algorithm of the DSC is configured such that during an initialization stage immediately following power up of the device relevant digital PWM modules used for interleaving operation are reconfigured to temporarily operate in an independent operation mode with the duty cycle associated with each channel set at zero. The reconfigured digital PWM modules remain set in the independent operation mode for a predefined period of time. Once the predefined time period is reached, the reconfigured digital PWM modules are again reconfigured back to the original complementary operation mode configuration and the control algorithm resumes normal operation of the DSC and digital PWM modules.

First claim

What is claimed is:

1. A method of eliminating random pulses during power up of a device, the method comprises:
a. configuring each of one or more digital pulse width modulators within a switching mode power supply to operate in an independent operation mode and a complementary operation mode;
b. at power up of the switching mode power supply, operating each digital pulse width modulator in the independent operation mode and continuing to operate each digital pulse width modulator in the independent operation mode for a predetermined period of time;
c. changing the operation of each digital pulse width modulator from the independent operation mode to the complementary operation mode after the predetermined period of time expires, wherein changing the operation occurs during an initialization stage; and
d. during a normal operation following the initialization stage, operating each digital pulse width modulator in the complementary operation mode.

2. The method of claim 1 further comprising monitoring a timing counter value and comparing the timing counter value to the predetermined period of time.

3. The method of claim 2 wherein the timing counter value is provided by a software counter.

4. The method of claim 1 wherein at least one of the one or more digital pulse width modulators includes multiple channels, each channel supplies a pulse width modulated signal having a defined duty cycle, wherein the one or more digital pulse width modulators are configured for power factor correction interleaving operation.

5. The method of claim 4 wherein the duty cycle of each channel is set to zero while in the independent operation mode during the initialization stage.

6. The method of claim 4 wherein during complementary operation mode a duty cycle of a first channel of the at least one digital pulse width modulator and a duty cycle of a second channel of the at least one digital pule width modulator are complementary of each other such that when the first channel is signal high the second channel is signal low, and when the first channel is signal low the second channel is signal high.

7. The method of claim 1 wherein each of one or more digital pulse width modulators generates a random pulse during power up if operating in the complementary operation mode instead of the independent operation mode.

8. A method of eliminating random pulses during power up of a device, the method comprises:
a. configuring a digital pulse width modulator within a switching mode power supply to operate in an independent operation mode and a complementary operation mode, wherein the digital pulse width modulator operates with a defined duty cycle for power factor correction interleaving operation;
b. at power up of the switching mode power supply, operating the digital pulse width modulator in the independent operation mode and continuing to operate the digital pulse width modulator in the independent operation mode for a predetermined period of time;
c. changing the operation of the digital pulse width modulator from the independent operation mode to the complementary operation mode after the predetermined period of time expires, wherein changing the operation occurs during an initialization stage; and
d. during a normal power factor correction interleaving operation following the initialization stage, operating the digital pulse width modulator in the complementary operation mode.

9. The method of claim 8 further comprising monitoring a timing counter value and comparing the timing counter value to the predetermined period of time.

10. The method of claim 9 wherein the timing counter value is provided by a software counter.

11. The method of claim 8 wherein the digital pulse width modulator includes multiple channels, each channel supplies a pulse width modulated signal having a defined duty cycle.

12. The method of claim 11 wherein the duty cycle of each channel is set to zero while in the independent operation mode during the initialization stage.

13. The method of claim 8 wherein the digital pulse width modulator generates a random pulse during power up if operating in the complementary operation mode instead of the independent operation mode.

14. An apparatus for eliminating random pulses during power up, the apparatus comprising:
a. one or more digital pulse width modulators each configured to operate in an independent operation mode and a complementary operation mode; and
b. a processor coupled to the one or more digital pulse width modulators, the processor comprises program instructions configured to:
i. at power up of the apparatus, operating each digital pulse width modulator in the independent operation mode and continuing to operate each digital pulse width modulator in the independent operation mode for a predetermined period of time;
ii. changing the operation of each digital pulse width modulator from the independent operation mode to the complementary operation mode after the predetermined period of time expires, wherein changing the operation occurs during an initialization stage; and
iii. during a normal operation following the initialization stage, operating each digital pulse width modulator in the complementary operation mode.

15. The apparatus of claim 14 wherein the program instructions are further configured to monitor a timing counter value and comparing the timing counter value to the predetermined period of time.

16. The apparatus of claim 15 wherein the apparatus further comprises a software counter and the timing counter value is provided by the software counter.

17. The apparatus of claim 14 wherein each digital pulse width modulator includes multiple channels, each channel supplies a pulse width modulated signal having a defined duty cycle, wherein the one or more digital pulse width modulators are configured for power factor correction interleaving operation.

18. The apparatus of claim 17 wherein the program instructions are further configured to set the duty cycle of each channel to zero while in the independent operation mode during the initialization stage.

19. The apparatus of claim 14 wherein normal operation comprises normal power factor correction interleaving operation.

20. The apparatus of claim 14 wherein each of the one or more digital pulse width modulators generates a random pulse during power up if operating in the complementary operation mode instead of the independent operation mode.

21. The apparatus of claim 14 wherein the processor comprises a digital signal controller or a microcontroller.

Assignees

• Flextronics Ap Llc

Inventors

• Ye Zhen Z

Classifications

• H02M1/36

  Means for starting or stopping converters · CPC title

• H02M2001/0012

  Electricity · mapped topic

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H02M1/4208

  Arrangements for improving power factor of AC input · CPC title

• H03K5/125

  Discriminating pulses (measuring characteristics of individual pulses G01R29/02; separation of synchronising signals in television systems H04N5/08) · CPC title