Liquid crystal display device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9323116-B2
Application number	US-201414330513-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Aug 29, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A pixel of an LCD device includes a gate line, a data line intersecting with the gate line, a gate insulation layer between the data line and the gate line, a thin film transistor formed at an intersection of the gate line and the data line, a planarization layer, a common electrode formed on the planarization layer, a pixel electrode formed over the common electrode, and an insulation layer between the common electrode and the pixel electrode. The common electrode is formed with groove extending along a region where the data line extends. Material of the common electrode is absent from the groove to reduce capacitance between the common electrode and the data line.

First claim

What is claimed is:

1. A liquid crystal display device comprising:
a gate line formed on an insulation substrate;
a data line formed to intersect with the gate line to define a pixel region;
a thin film transistor formed at an intersection of the gate line and the data line;
a planarization layer formed on the substrate, the data line and the thin film transistor;
a common electrode formed on the planarization layer, the common electrode formed with a plurality of perforations within a region corresponding to the data line, each of the perforations having a width smaller than a width of the data line, the plurality of perforations reducing capacitance between the data line and the common electrode;
a pixel electrode formed over the common electrode; and
a common line which is formed in a same layer and formed with a same material as the gate line and connected to the common electrode through a contact hole.

2. The liquid crystal display device of claim 1 , wherein the common electrode is formed over an entire pixel region.

3. The liquid crystal display device of claim 1 , wherein
the pixel electrode is connected to the thin film transistor through a contact hole, and
a groove is formed within a region of the contact hole for connecting the thin film transistor to the pixel electrode.

4. A method of fabricating a liquid crystal display device, the method comprising:
Forming, a common line, a gate line and a gate electrode branching from the gate line on an insulation substrate at a same time;
forming a gate insulation layer on the substrate formed with the gate line and the gate electrode;
forming a semiconductor layer, source and drain electrodes and a data line on the gate insulation layer;
forming a planarization layer on the substrate formed with the source and drain electrode and the data line;
forming a contact hole to connect the common electrode to the common line after forming the planarization layer;
forming, on the planarization layer, a common electrode;
forming a plurality of perforations in a region within the common electrode to reduce capacitance between the common electrode and the data line, each of the perforations having a width narrower than a width of the data line;
forming an insulation layer on the common electrode; and
forming a pixel electrode on the insulation layer.

5. The method of claim 4 , wherein a contact hole is formed after forming the insulation layer to connect the pixel electrode to the drain electrode.

6. The method of claim 5 , wherein the common electrode is formed to allow a groove to be formed within a region in the common electrode where the contact hole for connecting the pixel electrode and the drain electrode is formed.

7. A liquid crystal display device comprising an array of pixels, each of the pixels comprising:
a gate line;
a data line intersecting with the gate line to define a pixel region of each of the pixels in conjunction with the gate line; and
a common electrode formed with two rows of perforations extending along the data line, each of the perforations having a width narrower than a width of the data line, material of the common electrode absent from the perforations to reduce capacitance between the common electrode and the data line.

8. The liquid crystal display device of claim 7 , wherein each of the pixels further comprises a planarization layer between the data line and the common electrode.

9. The liquid crystal display device of claim 7 , wherein each of the pixels further comprises a thin film transistor at an intersection of the gate line and the data line, the thin film transistor comprising:
a gate electrode connected to the gate line,
a semiconductor layer over the gate electrode,
a source electrode connected to the data line, and
a drain electrode, the common electrode formed with a groove at a location corresponding to the drain electrode.

10. The liquid crystal display device of claim 9 , further comprising a pixel electrode connected to the drain electrode through a contact hole, and wherein the common electrode is formed with another groove in a region of the contact hole for connecting the thin film transistor to the pixel electrode.

11. The liquid crystal display device of claim 7 , further comprising a pixel electrode formed over the common electrode.

12. The liquid crystal display device of claim 7 , wherein each of the pixels is operated by fringe field switching (FFS).

13. The liquid crystal display device of claim 7 , wherein each of the pixels further comprises a common line formed with the same material as the gate line and connected to the common electrode through a contact hole.

14. A method of fabricating a liquid crystal display device, comprising:
forming a gate line on a substrate;
forming a gate insulation layer at least on the gate line;
forming a data line on the gate insulation layer;
forming a planarization layer over the substrate, gate line, and the data line;
forming, on the planarization layer, a common electrode within which two rows perforations are formed along the data line, each of the perforations having a width narrower than a width of the data line, material of the common electrode absent from the plurality of perforations to reduce capacitance between the common electrode and the data line.

15. The method of claim 14 , further comprising:
forming a common line in a same layer as the gate line, and
forming a contact hole for connecting the common electrode to the common line, after forming the planarization layer.

16. The method of claim 14 , wherein forming the common electrode comprises:
forming a metal layer on the planarization layer,
coating a photoresist over the formed metal layer, and
performing a photolithographic process using a mask on the formed metal layer coated with the photoresist.

17. The method of claim 14 , further comprising forming a pixel electrode after forming the common electrode.

18. The method of claim 17 , further comprising:
forming a gate electrode of a thin film transistor, the gate insulation layer formed on the gate electrode;
forming a drain electrode and a source electrode of the thin film transistor, the planarization layer formed on the drain electrode and the source electrode;
forming an insulation layer on the common electrode, the pixel electrode formed on the insulation layer; and
forming a contact hole for connecting the pixel electrode to the drain electrode after forming the insulation layer.

19. The method of claim 18 , wherein the common electrode is formed with a groove in a region where a contact hole for connecting the pixel electrode to the drain electrode is formed.

Assignees

• Lg Display Co Ltd

Inventors

• You Jae Hyun
• Shin Chul Sang

Classifications

• G02F1/134363 Primary

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F2001/134372

  Physics · mapped topic

• G02F2001/134318

  Physics · mapped topic

• G02F1/1343

  Electrodes {(reflective electrodes G02F1/133553)} · CPC title

• G02F1/136 Primary

  Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence) · CPC title