System and method for a phase detector

Patent metadata

Field	Value
Publication number	US-9322858-B2
Application number	US-201414172675-A
Country	US
Kind code	B2
Filing date	Feb 4, 2014
Priority date	Feb 4, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

First claim

What is claimed is:

1. A method of detecting a phase difference between a first signal and a second signal, the method comprising:
latching, using a first gated latch circuit, a state of the first signal using the second signal as a clock to produce a first latched signal, wherein the first gated latch circuit is transparent when the second signal is asserted, and the first gated latch circuit stores a value of the first signal when the second signal is not asserted;
latching, using a second gated latch circuit, a state of the second signal using the first signal as a clock to produce a second latched signal, wherein the second gated latch circuit is transparent when the first signal is asserted, and the second gated latch circuit stores a value of the second signal when the first signal is not asserted; and
summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

2. The method of claim 1 , further comprising inverting the second signal at a clock input of the second gated latch circuit.

3. The method of claim 1 , further comprising inverting the first latched signal prior to summing the first latched signal and the second latched signal.

4. The method of claim 1 , wherein summing comprises low pass filtering the first latched signal and the second latched signal.

5. The method of claim 4 , wherein low pass filtering comprises using an RC network.

6. The method of claim 1 , further comprising providing the first signal and the second signal from outputs of a directional coupler.

7. The method of claim 6 , further comprising detecting an amplitude of the first signal and an amplitude of the second signal.

8. The method of claim 1 , wherein the first gated latch circuit and the second gated latch circuit each comprise a differential data input and a differential clock input.

9. A circuit comprising a phase detector circuit, wherein the phase detector circuit comprises:
a first gated latch having a data input coupled to a first input of the phase detector circuit and a clock input coupled to a second input of the phase detector circuit, wherein the first gated latch is transparent when the clock input of the first gated latch is asserted, and the first gated latch stores a value of the data input of the first gated latch when the clock input of the first gated latch is not asserted;
a second gated latch having a data input coupled to the second input of the phase detector circuit and a clock input coupled to the first input of the phase detector circuit, wherein the second gated latch is transparent when the clock input of the second gated latch is asserted, and the second gated latch stores a value of the data input of the second gated latch when the clock input of the second gated latch is not asserted; and
a summing circuit having a first input coupled to an output of the first gated latch and a second input coupled to an output of the second gated latch, wherein an output of the summing circuit indicates whether a signal at the first input of the phase detector circuit is leading or lagging a signal at the second input of the phase detector circuit.

10. The circuit of claim 9 , wherein the first input of the summing circuit is coupled to an inverted output of the first gated latch, and the second input of the summing circuit is coupled to a non-inverted output of the second gated latch.

11. The circuit of claim 9 , further comprising an inverter circuit coupled between the output of the first gated latch and the first input of the summing circuit.

12. The circuit of claim 9 , wherein the clock input of the second gated latch is inverted with respect to the clock input of the first gated latch.

13. The circuit of claim 9 , further comprising an inverter circuit coupled between the second input of the phase detector circuit and the clock input of the first gated latch.

14. The circuit of claim 9 , wherein the summing circuit comprises:
a first series resistor coupled to an output of the first gated latch;
a second series resistor coupled to an output of the second gated latch; and
a load capacitor coupled to the first series resistor and the second series resistor.

15. The circuit of claim 9 , further comprising an RF coupler having a first output coupled to the first input of the phase detector circuit and a second output coupled to the second input of the phase detector circuit.

16. The circuit of claim 15 , further comprising a first power detector coupled to the first input of the phase detector circuit, and a second power detector coupled to the second input of the phase detector circuit.

17. A circuit comprising a phase detector circuit, wherein the phase detector circuit comprises:
a first gated latch having a data input coupled to a first input of the phase detector circuit and a clock input coupled to a second input of the phase detector circuit;
a second gated latch having a data input coupled to the second input of the phase detector circuit and a clock input coupled to the first input of the phase detector circuit; and
a summing circuit having a first input coupled to an output of the first gated latch and a second input coupled to an output of the second gated latch, wherein an output of the summing circuit indicates whether a signal at the first input of the phase detector circuit is leading or lagging a signal at the second input of the phase detector circuit, wherein the first gated latch and the second gated latch each comprise a differential data input and a differential clock input.

18. The circuit of claim 17 , wherein the first gated latch and the second gated latch each comprise:
a first differential pair of transistors having control nodes coupled to the differential clock input;
a second differential pair of transistors coupled to a first output of the first differential pair of transistors, the second differential pair of transistors having control nodes coupled to the differential data input; and
a third differential pair of transistors coupled to a second output of the first differential pair of transistors, wherein a control node of a first transistor of the third differential pair of transistors is coupled to an output node of a second transistor of the third differential pair of transistors, and a control node of the second transistor of the third differential pair of transistors is coupled to an output node of the first transistor of the third differential pair of transistors.

19. The circuit of claim 18 , wherein,
the first differential pair of transistors comprises a first differential pair of MOS transistors;
the second differential pair of transistors comprises a second differential pair of MOS transistors; and
the third differential pair of transistors comprises a third differential pair of MOS transistors.

20. The circuit of claim 17 , wherein:
the first gated latch and the second gated latch each further comprise a differential output; and
the summing circuit comprises
a first resistor coupled between a first terminal of the differential output of the first gated latch and a first output of the summing circuit,
a second resistor coupled between a second terminal of the differential output of the first gated latch and a second output of the summing circuit,
a third resistor coupled between a first terminal of the differential output of the second gated latch and the second output of the summing circuit, and
a fourth resistor coupled between a second terminal of

Assignees

• Infineon Technologies Ag
• Infineon Technologies Austria

Inventors

• Solomko Valentyn

Classifications

• G01R25/005 Primary

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title

• H04B1/40

  Circuits · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03D13/001

  in which a pulse counter is used followed by a conversion into an analog signal · CPC title