Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle, delayed signals

Patent metadata

Field	Value
Publication number	US-9319040-B2
Application number	US-201414580655-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Mar 12, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.

First claim

What is claimed is:

1. A method for controlling programmable delay signal logic, comprising:
setting a selector register of programmable delay signal logic to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory, wherein the programmable delay signal logic is programmable by the selector register value to receive a signal and output a delayed signal delayed by the required number of clock cycles of delay on a rising edge of a clock cycle from among 1 to N programmable clock cycles of delay;
controlling a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal, wherein the delay signal logic comprises at least one multiplexor distributed along a delay path of the delay signal logic, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs according to the value set in the selector register to control the required number of clock cycles of delay added to the signal from 1 to N clock cycles, wherein the at least one multiplexor comprises N−1 multiplexors, and at least two latches distributed along the delay path of the delay signal logic, wherein each at least one latch is configured to add a clock cycle of delay, wherein the at least two latches comprise N latches, wherein the signal is initially simultaneously distributed both as input to a first latch of the at least two latches positioned in the delay path and as one of the two inputs to each at least one multiplexor, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the required number of clock cycles; and
waiting the required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.

2. The method according to claim 1 , further comprising:
detecting a number of clock cycles of delay for signals output from an integrated circuit to the external memory; and
setting the selector register to the detected number of clock cycles as the required number of clock cycles of delay.

3. A system for controlling programmable delay signal logic, comprising:
a controller, implemented in at least one hardware component, operative to set a selector register of programmable delay signal logic to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory, wherein the programmable delay signal logic is programmable by the selector register value to receive a signal and output a delayed signal delayed by the required number of clock cycles of delay on a rising edge of a clock cycle from among 1 to N programmable clock cycles of delay;
the controller operative to control a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal, wherein the delay signal logic comprises at least one multiplexor distributed along a delay path of the delay signal logic, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs according to the value set in the selector register to control the required number of clock cycles of delay added to the signal from 1 to N clock cycles, wherein the at least one multiplexor comprises N−1 multiplexors, and at least two latches distributed along the delay path of the delay signal logic, wherein each at least one latch is configured to add a clock cycle of delay, wherein the at least two latches comprise N latches, wherein the signal is initially simultaneously distributed both as input to a first latch of the at least two latches positioned in the delay path and as one of the two inputs to each at least one multiplexor, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the required number of clock cycles; and
the controller operative to wait the required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.

4. The system according to claim 3 , further comprising:
the controller operative to detect a number of clock cycles of delay for signals output from an integrated circuit to the external memory; and
the controller operative to set the selector register to the detected number of clock cycles as the required number of clock cycles of delay.

5. A computer program product for controlling programmable delay signal logic, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
set a selector register of programmable delay signal logic to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory, wherein the programmable delay signal logic is programmable by the selector register value to receive a signal and output a delayed signal delayed by the required number of clock cycles of delay on a rising edge of a clock cycle from among 1 to N programmable clock cycles of delay;
control a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal, wherein the delay signal logic comprises at least one multiplexor distributed along a delay path of the delay signal logic, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs according to the value set in the selector register to control the required number of clock cycles of delay added to the signal from 1 to N clock cycles, wherein the at least one multiplexor comprises N−1 multiplexors, and at least two latches distributed along the delay path of the delay signal logic, wherein each at least one latch is configured to add a clock cycle of delay, wherein the at least two latches comprise N latches, wherein the signal is initially simultaneously distributed both as input to a first latch of the at least two latches positioned in the delay path and as one of the two inputs to each at least one multiplexor, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the required number of clock cycles; and
wait the required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.

6. The computer program product according to claim 5 , further comprising the program instructions executable by a processor to cause the processor to:
detect a number of clock cycles of delay for signals output from an integrated circuit to the external memory; and
set the selector register to the detected number of clock cycles as the required number of clock cycles of delay.

Assignees

• IBM

Inventors

• Dinh Huu N
• Horton Robert S
• On Bill N

Classifications

• H03K2005/00241

  using shift registers · CPC title

• H03K2005/00104

  using a reference signal, e.g. a reference clock · CPC title

• H03K19/1737

  using multiplexers (H03K19/1738 takes precedence) · CPC title

• H03K5/159 Primary

  Applications of delay lines not covered by the preceding subgroups · CPC title

• H03K3/037

  Bistable circuits · CPC title