Multi-level inverter with flying capacitor topology

Patent metadata

Field	Value
Publication number	US-9318974-B2
Application number	US-201414485682-A
Country	US
Kind code	B2
Filing date	Sep 13, 2014
Priority date	Mar 26, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

First claim

We claim:

1. An apparatus comprising:
a multi-level inverter comprising a first phase circuit and a second phase circuit, each of the first and the second phase circuits comprising a flying capacitor circuit;
a first set of switches connecting the first phase circuit between voltage input terminals and a second set of switches connecting the second phase circuit between the voltage input terminals; and
an interphase balancing circuit comprising a first pair of terminals connected in parallel across the first phase circuit and a second pair of terminals connected in parallel across the second phase circuit.

2. The apparatus of claim 1 , further comprising a controller, wherein:
the first phase circuit and the second phase circuit each comprise a phase output, an inductor, first and second pairs of switches and first and second capacitors;
a first terminal of the inductor is connected to the phase output;
a second terminal of the inductor is connected to first terminals of the first pair of switches;
the first capacitor is connected across junctions that connect second terminals of the first pair of switches respectively to first terminals of the second pair of switches;
the second capacitor is connected across second terminals of the second pair of switches; and
the controller is configured to balance a voltage across the first capacitor.

3. The apparatus of claim 1 , further comprising a controller, wherein:
the first set of switches comprises at least one high switch connecting a first input terminal of the first phase circuit to a first one of the voltage input terminals and least one low switch connecting a second input terminal of the first phase circuit to a second one of the voltage input terminal;
the second set of switches comprises at least one second high switch connecting a first input terminal of the second phase circuit to the first one of the voltage input terminals and least one second low switch connecting a second input terminal of the second phase circuit to the second one of the voltage input terminals; and
the controller is configured to switch the first set of switches and the second set of switches at a lower frequency than switches in first and second phase circuits.

4. The apparatus of claim 1 , wherein the interphase balancing circuit comprises:
a first switch connecting a high input terminal of the first phase circuit to a low input terminal of the second phase circuit; and
a second switch connecting a high input terminal of the second phase circuit to a low input terminal of the first phase circuit.

5. The apparatus of claim 1 , further comprising a controller circuit configured to control the first and the second sets of switches at a lower frequency than the first phase circuit and the second phase circuit.

6. The apparatus of claim 1 , wherein:
the first set of switches comprises a first plurality of high switches connected in series between a first input terminal of the first phase circuit and a first one of the voltage input terminals, and a first plurality of low switches connected in series between a second input terminal of the first phase circuit and a second one of the voltage input terminals; and
the second set of switches comprises a second plurality of high switches connected in series between a first input terminal of the second phase circuit and the first one of the voltage input terminals and a second plurality of low switches connecting a second input terminal of the second phase circuit to the second one of the voltage input terminals.

7. The apparatus of claim 1 , wherein the first phase circuit comprises:
a first bank and a second bank of series connected switches, wherein the first bank and the second bank are connected in series between the first set of switches; and
a plurality of capacitors each connected between one of the series connected switches in the first bank and a corresponding one of the series connected switches in the second bank.

8. The apparatus of claim 7 , further comprising:
a controller circuit configured to toggle each of a plurality of series connected switches in the first bank at a common duty cycle and at a common frequency, toggle each of the series connected switches in the first bank and its corresponding one of the series connected switches in the second bank in opposite states, and shift a phase of each of the plurality of series connected switches in the first bank by a sequentially increasing amount.

9. The apparatus of claim 8 , wherein the controller circuit is configured to adjust switching of at least one of the plurality of series connected switches to a different duty cycle such that voltage across one of the plurality of capacitors is compensated in response to mismatches between those of the series connected switches connected to the one of the plurality of capacitors.

10. The apparatus of claim 8 , wherein the controller circuit is configured to adjust the common duty cycle to adjust a conversion ratio of the multi-level inverter.

11. The apparatus of claim 1 , wherein the flying capacitor circuit of each of the first and the second phase circuits comprises series connected low voltage MOSFET transistors.

12. The apparatus of claim 11 , wherein the flying capacitor circuit of each of the first and the second phase circuits comprises a plurality of switched resistors, each switched resistor of the plurality of switched resistors bypassing one of the low voltage MOSFET transistors.

13. The apparatus of claim 1 , further comprising a controller circuit configured to switch the first and the second phase circuits at a cycle frequency of about 50 kHz or about 200 kHz.

14. The apparatus of claim 1 , further comprising:
one or more additional phase circuits, each comprising a flying capacitor circuit;
one or more additional sets of switches respectively connecting the one or more additional phase circuits between the voltage input terminals; and
one or more additional pairs of terminals comprised in the interphase balancing circuit and respectively connected across the one or more additional phase circuits.

15. The apparatus of claim 1 , further comprising a transformer comprising:
a first winding coupled across an output of the first phase circuit and an output of the second phase circuit; and
a second winding forming a phase output of the apparatus.

16. The apparatus of claim 1 , further comprising first and second transformers, wherein a first winding of the first transformer is conductively coupled to an output of the first phase circuit and a first winding of the second transformer is conductively coupled to an output of the second phase circuit; and a second winding of the first transformer and a second winding of the second transformer form phase outputs of the apparatus.

17. The apparatus of claim 1 , wherein the first phase circuit comprises first phase input terminals connected to the first set of switches and to the first pair of terminals of the interphase balancing circuit, and wherein the second phase circuit comprises second phase input terminals connected to the second set of switches and to the second pair of terminals of the interphase balancing circuit.

18. A method comprising:
switching a first phase circuit and a second phase circuit of a multilevel inverter at a first frequency;
switching a first pair of switches and a second pair of switches of the multilevel inverter at a second frequency, the first pair of switches connecting the first phase circuit between a pair of voltage input terminals and the second pair of switche

Assignees

• Solaredge Technologies Ltd
• Solaredge Technologies Ltd

Inventors

• Yoscovich Ilan
• Glovinsky Tzachi
• Sella Guy
• Galin Yoav

Classifications

• H02M7/537 Primary

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M1/126

  using passive filters · CPC title

• H02M7/483 Primary

  Converters with outputs that each can have more than two voltages levels · CPC title

• H02M2007/4835

  Electricity · mapped topic

• H02M7/4835

  comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage · CPC title